DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10, 13-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su (U.S. Publication No. 2023/0104966 A1; hereinafter Su) in view of Shepard et al. (U.S. Publication No. 2016/0240692 A1; hereinafter Shepard)
With respect to claim 1, Su discloses a semiconductor transistor device, comprising: a substrate [311]; a 2D nanosheet layer [312] disposed onto the substrate; a source region [313]; and a drain region [314]; and wherein the 2D nanosheet layer provides a conducting path between the source region and the drain region (see Figure 10) of the transistor device.
Su fails to disclose wherein the 2D nanosheet layer is a 2D silicon carbide nanosheet layer. In the same field of endeavor, Shepard teaches a 2D silicon carbide nanosheet [602] channel as alternatives to the materials as disclosed by Su (See Figure 6 and ¶[0075]). Implementation of silicon carbide allows for improvements in carrier mobility and density (see Shepard ¶[0097]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Su and Shepard discloses wherein the 2D silicon carbide nanosheet layer is a channel layer (See Su Figure 10 and Shepard ¶[0084]).
With respect to claim 3, the combination of Su and Shepard discloses wherein a thickness of the 2D silicon carbide nanosheet layer is from about 0.25 nm to about 25 nm (see Su ¶[0043]). With respect to claim 4, the combination of Su and Shepard discloses wherein the 2D silicon carbide nanosheet layer comprises a single layer (see Su Figure 10 and Shepard Figure 6 and ¶[0058]; “comprises” allows for at least one single layer versus only a single layer).
With respect to claim 5, the combination of Su and Shepard discloses wherein the 2D silicon carbide nanosheet layer comprises from about 1 to about 5 layers (see Su Figure 10; [3121,3122,3123]).
With respect to claim 6, the combination of Su and Shepard discloses wherein the 2D silicon carbide nanosheet layer comprises from about 10 to about 100 layers (see Su ¶[0052] and Shepard ¶[0057]; any number of nanosheets can be formed in the stack of layers).
With respect to claim 7, the combination of Su and Shepard discloses a planar structure (see Su Figure 10; Shepard Figure 6).
With respect to claim 8, the combination of Su and Shepard discloses a stacked design; and more than one gate layer (See Su Figure 12).
With respect to claim 9, the combination of Su and Shepard discloses wherein the semiconductor device is a transistor (See Su Figure 10).
With respect to claim 10, the combination of Su and Shepard discloses wherein the semiconductor device is a MOSFET (See Su ¶[0076]).
With respect to claim 13, Su discloses a semiconductor device, comprising: a substrate [311]; at least one epitaxial layer [3211] disposed onto the substrate (See ¶[0065]); a channel layer [322] comprising one or more 2D nanosheets, disposed onto the at least one epitaxial layer; a source region [323] in contact with the channel layer of the transistor device; and a drain region [324] in contact with the channel layer of the transistor device (See Figure 11).
Su fails to disclose wherein the 2D nanosheet layer is a 2D silicon carbide nanosheet layer. In the same field of endeavor, Shepard teaches a silicon carbide nanosheet channel as alternatives to the materials as disclosed by Su (See Figure 6 and ¶[0075]). Implementation of silicon carbide allows for improvements in carrier mobility and density (see Shepard ¶[0097]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 14, the combination of Su and Shepard discloses wherein a thickness of the 2D silicon carbide nanosheet channel layer is from about 0.25 nm to about 25 nm (see Su ¶[0043]).
With respect to claim 15, the combination of Su and Shepard discloses wherein the 2D silicon carbide nanosheet layer comprises from about 1 to about 100 layers (see Su Figure 11; [3221,3222,3223] and Shepard ¶[0057]).
With respect to claim 16, the combination of Su and Shepard discloses wherein the semiconductor device is a transistor (See Su Figure 10-11)
With respect to claim 17, the combination of Su and Shepard discloses wherein the semiconductor device is a MOSFET (See Su ¶[0076]).
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su in view of Shepard as applied to claims 11 and 13 above, and further in view of Seo et al. (U.S. Publication No. 2023/0422577 A1; hereinafter Seo)
With respect to claim 11, the combination of Su and Shepard fails to disclose wherein the semiconductor device is a light-emitting diode but does acknowledge utilization of nanosheets within an LED (See ¶[0002]). In the same field of endeavor, Seo teaches an LED with transistor structures. Implementation of the transistors of the combination of Su and Wang within the LEDs of Seo allows for the utilization of the high carrier mobility of the transistors within the LED device (see ¶[0469]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 12, the combination of Su, Shepard and Seo discloses wherein the light-emitting diode is a blue light-emitting diode (See Seo ¶[0074]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (U.S. Publication No. 2022/0165842 A1; hereinafter Wang) in view of Shepard.
With respect to claim 20, Wang discloses a semiconductor device, comprising: a substrate [101]; a channel layer [106/108] comprising silicon carbide nanosheets (see ¶[0023]), disposed onto the substrate; a source region [146] in contact with the channel layer of the transistor device; a drain region [146] in contact with the channel layer of the transistor device; at least one insulating layer [148] in contact with the channel layer of the transistor device; and at least one gate oxide layer [150] in contact with the at least one insulating layer; and wherein the channel layer comprises from about 1 to about 100 layers (See Wang ¶[0032]). Wang fails to explicitly disclose 2D nanosheets, however does disclose nanosheet dimensions (see ¶[0024]). In the same field of endeavor, Shepard teaches 2D silicon carbide nanosheets [602] channel (See Figure 6 and ¶[0075]). Implementation of silicon carbide allows for improvements in carrier mobility and density (see Shepard ¶[0097]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Response to Arguments
Applicant's arguments filed 03/20/2026 have been fully considered but they are not persuasive. With respect to arguments made in regards to claim 1, Applicant argues that the combination of references would arrive at the claimed invention of Su and Shepard fails to disclose “ a 2D silicon carbide nanosheet layer.” Applicant affirms that Shepard teaches a silicon-carbide alternative but argues that the listing does not teach that silicon carbide should be selected for a transistor channel. Examiner respectfully disagrees. Shepard addresses material alternatives to constructing a two dimensional channel structure (see ¶[0084]). Furthermore, Shepard explicitly discloses changes in resistivity as a function of back gate voltage (see Figure 23). While Shepard does not utilize the word “transistor,” Shepard’s device is a transistor based on the standard language of the art. Furthermore, Shepard’s list of alternative materials includes materials utilized by Su to produce the 2D layer which includes silicon carbide as Applicant affirms. The examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, as materials utilized in a channel structure are discussed in both prior art, one of ordinary skill in the art would appreciate the ability test the advantages of silicon carbide within the channel structure of Su.
Applicant further argues that Shepard’s characterization is also incorrect because Shepard discusses “this graphene device” and not “a device incorporating silicon-carbide. Furthermore, Applicant argues that Su is silent to any teachings of a transistor utilizing a 2D layer. Examiner respectfully disagrees. Shepard explicitly discloses that silicon-carbide is a functional alternative to be utilized (paragraph reproduced below). [0075] In another aspect, the presently disclosed subject matter provides a heterostructure. An exemplary embodiment of a heterostructure in accordance with the disclosed subject matter is illustrated in FIG. 6. The heterostructure 600 includes a first two dimensional layer 602 comprising an electrical contact 604 disposed on a one-dimensional edge thereof. The electrical contact 604 can be disposed on the edge of the two-dimensional layer 602 in accordance with the methods disclosed herein. The first two-dimensional layer 602 can be constructed from any suitable material including, for example and without limitation, graphene, hexagonal boron nitride, transition metal dichalcogenides, molybdenum disulfide, germanane, silicene, and silicon carbide. The electrical contact 604 can be constructed of one or more metals including chromium, palladium, gold, titanium, nickel, and aluminum. Applicant’s characterization of Shepard ignores explicit teachings within the prior art of alternatives and Shepard’s teachings are not isolated to a single example disclosed within the prior art. Furthermore, Su also discloses the utilization of graphene as a 2D material and therefore any characterization that Shepard and Su are not able to be combined is unfounded. Applicant ignores explicitly teachings by Su of utilizing 2D material as a semiconductor channel material (See ¶[0073]) and ignores teachings of Su that the 2D components can be integrated within multiple types of FET (field effect transistors) (see ¶[0075-0076]; reproduced below). [0075] Referring to FIG. 11, it is a schematic longitudinal sectional view of an electronic component 320 according to a second configuration of the invention, the electronic component 320 incorporating the artificial 2D material of the invention. The electronic component 320 is implemented as a back-gated FET in which a highly doped substrate 321 (e.g., P.sup.++ or N.sup.++Si) is used as a fin. The method of manufacturing the electronic component 320 comprises the steps of depositing a gate insulating layer 3211 (e.g., Al.sub.2O.sub.3, SiO.sub.2, nitride, or fluoride (e.g., CaF)); forming the artificial 2D material layer 322 including a middle atomic layer 3121, a lower atomic layer 3222 below the middle atomic layer 3221, and an upper atomic layer 3223 on the middle atomic layer 3221. The upper atomic layer 3223 is heterogeneous and includes a first heterogeneous zone 32231 and a second heterogeneous zone 32232 spaced from the first heterogeneous zone 32231. In the embodiment, the first and second heterogeneous zones 32231, 32232 each implemented as a metal atomic layer. The source 323 is provided on the second heterogeneous zone 32232 and the drain 324 is provided on the first heterogeneous zone 32231 respectively. Each of the source 323 and the drain 324 are metallic electrodes. Thus, the source 323 is electrically connected to the metal atomic layer of the second heterogeneous zone 32232 by means of metallic bonding and the drain 324 is electrically connected to the metal atomic layer of the first heterogeneous zone 32231 by means of metallic bonding respectively. The method of manufacturing the electronic component 320 further comprises the steps of using photolithography and deposition to form the channel on the gate insulating layer 3211; finally using hydrogen plasma to remove the upper metal layers, materials using ALE and then conjugation with metal based on the source 323 and the drain 324, thereby producing the electronic component 320. [0076] Above electronic components further comprise FinFET, gate-all-around FET (GAAFET), stacked nanosheet FET, and multi-bridge channel FET (MBCFET). Above characteristics are related to selectively remove atomic layers from the source and the drain to decrease their contact resistance. Regarding heterogeneous junctions, above manufacturing process can be used to synthesize a gate insulating layer as a structure of next generational as GAAFET. GAAFETs can inhibit leakage current and have better channel control. But the thin channel of GAAFET limits current density. Also, a vertical multi-channel limits height and causes interference with internal connection layers. Further, parasite capacitance adversely affects switching rate. The main bottleneck is that the manufacturing steps of the nanoscale GAAFET are more complicated and in turn it greatly increases the manufacturing cost and lowers yield. Thus, a stacked nanosheet FET is considered to be the optimum scheme for solve above problems. However, regarding the manufacturing of the stacked nanosheet FET, a Si/SiGe super lattice is used to selectively remove SiGe from the stacked nanosheet FET to obtain a suspended nanoscale element of Si. Next, ALD is performed to deposit a dielectric layer and a gate metal layer. But there is challenge to conformal coating of ALD and is different from the steps of the conventional CMOS process. Further, both nanosheet and GAAFET require an atomic layer deposition to fill gaps in the suspended lower layer. However, it greatly increases difficulties of manufacturing the semiconductor devices. Further, there is no disclosure about using 2D semiconductor to verify the structure of the semiconductor devices. Applicant further argues that Applicant’s 2D SiC disclosure is not the same as that of Su or Shepard, Examiner notes that In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., excellent oxidation stability and a graphene-like honeycomb structure consisting of alternating Si and C atoms) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Applicant further presents arguments regarding claim 20 and argues that Wang does not disclose a channel layer comprising 2D silicon nanosheets. Examiner agrees that Wang does not explicitly disclose 2D nanosheets but Applicant also omits that Examiner had disclosed that Wang does disclose nanosheet channels, specifically SiC nanosheet channels [0023] The stack of layers 104 includes alternating semiconductor layers made of different materials to facilitate formation of nanosheet channels in a multi-gate device, such as nanosheet channel FETs. In some embodiments, the stack of layers 104 includes first semiconductor layers 106 (106a-106c) and second semiconductor layers 108 (108a-108c). In some embodiments, the stack of layers 104 includes alternating first and second semiconductor layers 106, 108. The first semiconductor layers 106 are aligned with the second semiconductor layers 108. The first semiconductor layers 106 and the second semiconductor layers 108 are made of semiconductor materials having different etch selectivity and/or oxidation rates. For example, the first semiconductor layers 106 may be made of Si and the second semiconductor layers 108 may be made of SiGe. In some examples, the first semiconductor layers 106 may be made of SiGe and the second semiconductor layers 108 may be made of Si. In some cases, the SiGe in the first or second semiconductor layers 106, 108 can have a germanium composition percentage between about 10% and about 50%. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combinations thereof. Wang discloses a nanosheet transistor utilizing SiC nanosheets for channels. As previously discussed above, Applicant affirms that Shepard teaches a silicon-carbide 2D nanosheet channel. Examiner respectfully disagrees. Shepard addresses material alternatives to constructing a two dimensional channel structure (see ¶[0084]). Furthermore, Shepard explicitly discloses changes in resistivity as a function of back gate voltage (see Figure 23). While Shepard does not utilize the word “transistor,” Shepard’s device is a transistor based on the standard language of the art. The examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, as materials utilized in a channel structure are discussed in both prior art, one of ordinary skill in the art would appreciate the ability to utilize a 2D silicon carbide nanosheet of Shepard for a silicon carbide nanosheet of Wang.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN LOKE can be reached at 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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