Prosecution Insights
Last updated: August 18, 2026
Application No. 18/307,620

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103§112
Filed
Apr 26, 2023
Priority
Nov 24, 2022 — RE 10-2022-0158848
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
2 (Non-Final)
40%
Grant Probability
Moderate
2-3
OA Rounds
1m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 40% of resolved cases
40%
Career Allowance Rate
154 granted / 384 resolved
-27.9% vs TC avg
Strong +31% interview lift
Without
With
+31.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
52 currently pending
Career history
453
Total Applications
across all art units

Statute-Specific Performance

§103
43.8%
+3.8% vs TC avg
§102
16.1%
-23.9% vs TC avg
§112
35.1%
-4.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 384 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 3 and 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 3, the limitation “the first halogen element and the second halogen element are different from each other” does not appear to have adequate support in the originally filed disclosure, in particular in combination with the required concentrations of claim 1 and 2. Further, the combinations of features is not described in the original disclosure in such a way to convey possession. Specifically, this aspect of the claimed invention has not been described with sufficient particularity such that one skilled in the art would recognize that the inventor had possession of the claimed invention at the time of filing. The feature appears to be an essential or critical feature which is not adequately described in the specification and is not conventional or known in the art. (see MPEP 2163.A) It is noted that the only disclosure related to the concentrations is Fig. 2 and related text. The disclosure related to Fig. 2, however, has not been described in combination with C1 and C2 being different halogen elements, nor has it been sufficiently described how one could even achieve a concentration gradient including C1 and C2, wherein C2 is from a different halogen element than C1, and yet also is a continuation of the concentration curve throughout the layers (i.e. how C2 could, without a transitional region, abruptly be a second halogen at that concentration when immediately prior to the interface the C1 is entirely the first halogen). Regarding claim 15, the limitation “wherein the first halogen element, the second halogen element, and the third halogen element are different from each other, the first halogen element, the second halogen element, or the third halogen element includes at least one of fluorine (F) and chlorine (Cl)” does not appear to have adequate support in the originally filed disclosure. Specifically, only two possible halogens are disclosed, and thus it is unclear how each can be different from the other. Additionally, there does not appear to be support for the different halogens in combination with the required concentrations of claim 11. Further, the combinations of features is not described in the original disclosure in such a way to convey possession. Specifically, this aspect of the claimed invention has not been described with sufficient particularity such that one skilled in the art would recognize that the inventor had possession of the claimed invention at the time of filing. The feature appears to be an essential or critical feature which is not adequately described in the specification and is not conventional or known in the art. (see MPEP 2163.A) It is noted that the only disclosure related to the concentrations is Fig. 2 and related text. The disclosure related to Fig. 2, however, has not been described in combination with C1 and C2 being different halogen elements, nor has it been sufficiently described how one could even achieve a concentration gradient including C1 and C2, wherein C2 is from a different halogen element than C1, and yet also is a continuation of the concentration curve throughout the layers (i.e. how C2 could, without a transitional region, abruptly be a second halogen at that concentration when immediately prior to the interface the C1 is entirely the first halogen). The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 1-10 and 12, and 15 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the limitation “wherein the channel layer includes a first portion whose concentration of a first halogen element increases as the first portion becomes closer to the memory layer and a second portion whose concentration of the first halogen element increases as the second portion becomes closer to the silicide layer” is unclear as to how it is related to the previously recited “wherein at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element.” Specifically, it is unclear if the limitation is a conditional limitation in the instance that the channel layer is the “at least one of the channel layer, the silicide layer, and the memory layer includ[ing] a halogen element,” if the claim intends to require the channel layer to be the “at least one of the channel layer, the silicide layer, and the memory layer includ[ing] a halogen element,” or if the claim intends to require the channel layer to have the first halogen element in addition to the “at least one of the channel layer, the silicide layer, and the memory layer includ[ing] a halogen element.” It is further unclear as to how the “first halogen element” is related to the “a halogen element.” Regarding claim 1, the limitations “as the first portion becomes closer to the memory layer,” and “as the second portion becomes closer to the silicide layer” are unclear as to what is required by the limitations. Specifically, it appears to require the portion to move closer to the respective layer, which is not understood as possible in a device claim. Regarding claim 2, the limitation “wherein the channel layer includes the first halogen element at a first concentration, and an interface between the channel layer and the memory layer includes a second halogen element at a second concentration higher than the first concentration,” is unclear as to how the “the memory layer includes a second halogen element at a second concentration higher than the first concentration,” is related to “wherein at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element,” recited in claim 1. It is further unclear as to how “a first concentration” is related to the concentration of the first and second portions recited in claim 1. the “second halogen” is related to the “a halogen element”. Regarding claim 3, the limitation “the first halogen element and the second halogen element are different from each other” is unclear as to how it is related to the required concentrations of claim 1 and 2. Specifically, it is noted that the only disclosure related to the concentrations is Fig. 2 and related text. However the disclosure related to Fig. 2 not been described in combination with C1 and C2 being different halogen elements, nor has it been sufficiently described how one could even achieve a concentration gradient including C1 and C2, wherein C2 is from a different halogen element than C1, and yet also be a continuation of the concentration curve throughout the layers (i.e. how C2 could, without a transitional region, abruptly be a second halogen at that concentration when immediately prior to the interface the C1 is entirely the first halogen). Accordingly, it is unclear what the claimed limitation requires. Regarding claim 6, the limitation “a second halogen element is located at an interface between the channel layer and the memory layer,” is unclear as to how it is related to “wherein at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element,” recited in claim 1. Regarding claim 7, the limitation “a third halogen element is located at an interface between the channel layer and the silicide layer,” is unclear as to how it is related to “wherein at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element,” recited in claim 1. It is further unclear because it recites “a third halogen element,” when a second halogen has not been recited. Regarding claim 8, the limitation “wherein at least one of the tunneling layer, the data storage layer, and the blocking layer includes a second halogen element,” is unclear as to how it is related to “wherein at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element,” recited in claim 1. Regarding claim 9, the limitation “wherein the tunneling layer includes the second halogen element at a third concentration, and an interface between the tunneling layer and the channel layer includes the second halogen element at a fourth concentration higher than the third concentration,” is unclear as to how it is related to “wherein at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element,” recited in claim 1. It is further unclear because it recites “a third (fourth) concentration,” when a first and second concentration have not been recited. Regarding claim 15, the limitation “wherein the first halogen element, the second halogen element, and the third halogen element are different from each other, the first halogen element, the second halogen element, or the third halogen element includes at least one of fluorine (F) and chlorine (Cl)” is unclear how each of the halogens can be different when only two possible halogens are disclosed. Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Isogai et al. (US 20190081144; herein “Isogai”). Regarding claim 11, Isogai discloses in Figs. 2 and 4-5 and related text a semiconductor device comprising: a gate structure (e.g. 40/41, see [0047]) including insulating layers and conductive layers that are alternately stacked; a channel layer (20, see [0054]) located in the gate structure and including a first halogen element at a first concentration (e.g. concentration close to, but not at, interface between Rch and Rtn, see Fig. 5 and [0055]); a memory layer (e.g. 21/22/23, see [0035]) surrounding the channel layer and including a second halogen element at a second centration (e.g. concentration at middle of Rt1) lower than the first concentration; and an insulating core (25, see [0054]) located on the channel layer, wherein an interface between the channel layer and the memory layer includes a third halogen element at a third concentration (e.g. concentration at interface between Rch and Rtn) higher than the first concentration and the second concentration (see Fig. 5). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-2, 4-10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Isogai in view of Nakajima et al. (US 20200303405; herein “Nakajima”). Regarding claim 1, Isogai discloses in Figs. 4-5 and related text a semiconductor device comprising: a gate structure (e.g. 40/41, see [0047]) including insulating layers and conductive layers that are alternately stacked; a channel layer (20, see [0054]) located in the gate structure; a memory layer (e.g. 21/22/23, see [0035]) surrounding the channel layer; and wherein at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element (see Fig. 5 and [0055]); and wherein the channel layer includes a first portion whose concentration of a first halogen element increases as the first portion becomes closer to the memory layer and a second portion whose concentration of the first halogen element increases as the second portion becomes further from the memory layer (see Rch in Fig. 5). Isogai does not explicitly disclose a silicide layer located on the channel layer; the second portion whose concentration of the first halogen element increases as the second portion becomes closer to the silicide layer. In the same field of endeavor, Nakajima teaches in Fig. 5 and related text a semiconductor device comprising a silicide layer (99, see [0048]) located on the channel layer (44, see [00448]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Isogai by having a silicide layer located on the channel layer in order to provide a low resistance electrical contact to the channel layer. The limitation “the second portion whose concentration of the first halogen element increases as the second portion becomes closer to the silicide layer” is taught by the combination of the second portion whose concentration of the first halogen element increases as the second portion becomes further from the memory layer, as shown by Isogai, and the silicide layer being on the far side of the channel from the memory layer, as shown by Nakajima. Regarding claim 2, Isogai further discloses wherein the channel layer includes the first halogen element at a first concentration, and an interface between the channel layer and the memory layer includes a second halogen element at a second concentration higher than the first concentration (see Fig. 5, concentration at interface between Rch and Rtn higher than concentration at other regions in channel layer). Regarding claim 4, the combined device shows wherein the first portion is located closer to the memory layer than the second portion (Isogai: closer to Rtn of memory layer). Regarding claim 5, Isogai further discloses wherein the halogen element includes at least one of fluorine (F) and chlorine (Cl) (see [0055]). Regarding claim 6, Isogai further discloses wherein a second halogen element is located at an interface between the channel layer and the memory layer (see Fig. 5, concentration at interface between Rch and Rtn). Regarding claim 7, the combined device shows wherein a third halogen element is located at an interface between the channel layer and the silicide layer (see Fig. 5, concentration at interface of Rch and Rco; modified by Nakajima to include silicide on channel layer). Regarding claim 8, Isogai further discloses a tunneling layer (21, see [0035]) surrounding the channel layer; a data storage layer (22, see [0035]) surrounding the tunneling layer; and a blocking layer (23, see [0035]) surrounding the data storage layer, wherein at least one of the tunneling layer, the data storage layer, and the blocking layer includes a second halogen element (see Fig. 5). Regarding claim 9, Isogai further discloses wherein the tunneling layer includes the second halogen element at a third concentration, and an interface between the tunneling layer and the channel layer includes the second halogen element at a fourth concentration higher than the third concentration (e.g. concentration in Rt1 compared to at interface between Rtn and Rch, see Fig. 5). Regarding claim 10, the combined device shows an insulating core located on the silicide layer (Nakajima: 45, see [0048]). Regarding claim 12, Isogai discloses the invention as applied to claim 11 above, but does not explicitly disclose a silicide layer located between the channel layer and the insulating core. In the same field of endeavor, Nakajima teaches in Fig. 5 and related text a semiconductor device comprising a silicide layer (99, see [0048]) located between the channel layer and the insulating core (e.g. between 44 and 45 in at least one direction, see [00448]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Isogai by having a silicide layer located between the channel layer and the insulating core in order to provide a low resistance electrical contact to the channel layer. Response to Arguments Applicant's arguments filed 4/13/2026 have been fully considered but they are not persuasive. Applicant argues (page 13) that the prior art does not teach or suggest the invention of claim 11 because the concentration of halogen in layers 21/22/23 of Isogai is higher than the concentration of channel layer 20. In response, the examiner disagrees. Specifically, the concentration in channel layer 20 near (but not at) the interface between Rch and Rt1 is higher than the concentration at, e.g., the middle of Rt1. It is noted that the claim does not require the concentration throughout the entirety of the channel layer to be higher than the concentration throughout the entirety of the memory layer, nor is this relationship even support by applicant’s disclosure. Applicant’s remaining arguments are moot in view of the new grounds of rejection presented above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Apr 26, 2023
Application Filed
Dec 02, 2025
Response Filed
Jan 13, 2026
Non-Final Rejection mailed — §102, §103, §112
Apr 13, 2026
Response Filed
Jun 04, 2026
Final Rejection mailed — §102, §103, §112
Aug 05, 2026
Response after Non-Final Action

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Prosecution Projections

2-3
Expected OA Rounds
40%
Grant Probability
72%
With Interview (+31.4%)
3y 5m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 384 resolved cases by this examiner. Grant probability derived from career allowance rate.

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