Prosecution Insights
Last updated: April 19, 2026
Application No. 18/307,620

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103§112
Filed
Apr 26, 2023
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
1 (Non-Final)
40%
Grant Probability
At Risk
1-2
OA Rounds
3y 7m
To Grant
70%
With Interview

Examiner Intelligence

Grants only 40% of cases
40%
Career Allow Rate
148 granted / 375 resolved
-28.5% vs TC avg
Strong +31% interview lift
Without
With
+30.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
61 currently pending
Career history
436
Total Applications
across all art units

Statute-Specific Performance

§103
42.1%
+2.1% vs TC avg
§102
19.7%
-20.3% vs TC avg
§112
33.1%
-6.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 375 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, Group 1 - Species E, and Group 2 – Species B, in the reply filed on 12/2/2025 is acknowledged. Claims 13-14 and 16-35 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/2/2025. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 1-10 and 12, and 15 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the limitation “a silicide layer located in the channel layer” is unclear as to the meaning of “in.” Specifically, the silicide layer appears to be shown and disclosed as a separate layer from the channel layer but is described as both “in” and “between” with the specification seemingly equating the two terms (see [0026]). Accordingly, it is unclear what is required by the claim. Regarding claim 2, the limitation “the halogen at a second concentration” is unclear as to if it is the same halogen or a second halogen. Applicant asserts the claim reads on the elected species, which includes a first halogen concentration in the channel being less than a second halogen concentration at interface between the channel layer and the memory layer, with the first and second halogens being different, however the language “the halogen” would appear to require the same halogen. Regarding claim 6, the limitation “the halogen element is located at an interface between the channel layer and the memory layer,” is unclear as to if it is the same halogen or a second halogen. Applicant asserts the claim reads on the elected species, which includes a first halogen concentration in the channel being less than a second halogen concentration at interface between the channel layer and the memory layer, with the first and second halogens being different, however the language “the halogen” would appear to require the same halogen. Regarding claim 8, the limitation “wherein at least one of the tunneling layer, the data storage layer, and the blocking layer includes the halogen element,” is unclear as to if it is addition to the “wherein at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element,” recited in claim 1 or if it is intended to further specify the halogen of claim 1 is in the memory layer. Regarding claim 9, the limitations “a second (third) concentration” are unclear because they are dependent on a claim which does not recite a first concentration. Regarding claim 9, the limitation “the tunneling layer includes the halogen element at a third concentration, and an interface between the tunneling layer and the channel layer includes the halogen element at a second concentration higher than the third concentration,” is unclear as to if it is the same halogen or a second halogen. Applicant asserts the claim reads on the elected species, which includes a second halogen at a second concentration, different from the first halogen, at interface between the channel layer and the memory layer. The language “the halogen,” would appear to require the same halogen as that in the channel, however it is unclear as to if, in the elected embodiment, the halogen in the tunneling layer is the same or different as the second halogen at the second concentration, and as to what the relative concentrations would be. Regarding claim 12, the limitation “a silicide layer located between the channel layer and the insulating core” is unclear as to the meaning of “in.” Specifically, the silicide layer appears to be shown and disclosed as a separate layer from the channel layer but is described as both “in” and “between” with the specification seemingly equating the two terms (see [0026]). Accordingly, it is unclear what is required by the claim. Regarding claim 15, the limitation “substantially same or different,” is unclear as to what it means to be “substantially same” or “substantially different.” Additionally, the term “substantially” is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 11 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Isogai et al. (US 20190081144; herein “Isogai”). Regarding claim 11, Isogai discloses in Figs. 2 and 4-5 and related text a semiconductor device comprising: a gate structure (e.g. 40/41, see [0047]) including insulating layers and conductive layers that are alternately stacked; a channel layer (20, see [0054]) located in the gate structure and including a first halogen element at a first concentration (see Fig. 5 and [0055]); a memory layer (e.g. 21/22/23, see [0035]) surrounding the channel layer; and an insulating core (25, see [0054]) located in the channel layer, wherein an interface between the channel layer and the memory layer includes a second halogen element at a second concentration higher than the first concentration (see Fig. 5, concentration at interface between Rch and Rtn higher than concentration at other regions in channel layer). Regarding claim 15, Isogai further discloses wherein the first halogen element and the second halogen element are substantially same or different, the first halogen element or the second halogen element includes at least one of fluorine (F) and chlorine (Cl) (see Fig. 5 and [0055]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Isogai in view of Jang et al. (US 20220020766; herein “Jang”). Regarding claim 1, Isogai discloses in Figs. 4-5 and related text a semiconductor device comprising: a gate structure (e.g. 40/41, see [0047]) including insulating layers and conductive layers that are alternately stacked; a channel layer (20, see [0054]) located in the gate structure; a memory layer (e.g. 21/22/23, see [0035]) surrounding the channel layer; and wherein at least one of the channel layer, the silicide layer, and the memory layer includes a halogen element (see Fig. 5 and [0055]). Isogai does not explicitly disclose a silicide layer located in the channel layer. In the same field of endeavor, Jang teaches a semiconductor device comprising a silicide layer located in the channel layer (see [0085]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Isogai by having a silicide layer located in the channel layer in order to employ a method of manufacture which assists and improves crystallization of the channel layer. Regarding claim 2, Isogai further discloses wherein the channel layer includes the halogen element at a first concentration, and an interface between the channel layer and the memory layer includes the halogen element at a second concentration higher than the first concentration (see Fig. 5, concentration at interface between Rch and Rtn higher than concentration at other regions in channel layer). Regarding claim 3, the combined device shows wherein the channel layer comprises: a first portion whose concentration of the halogen element increases as the first portion becomes closer to the memory layer (Isogai: closer to Rtn, see Fig. 5 and related text); and a second portion whose concentration of the halogen element increases as the second portion becomes closer to the silicide layer (Isogai: closer to Rch, see Fig. 5 and related text). Regarding claim 4, the combined device shows wherein the first portion is located closer to the memory layer than the second portion (Isogain: closer to Rtn of memory layer). Regarding claim 5, Isogai further discloses wherein the halogen element includes at least one of fluorine (F) and chlorine (Cl) (see [0055]). Regarding claim 6, Isogai further discloses wherein the halogen element is located at an interface between the channel layer and the memory layer (see Fig. 5, concentration at interface between Rch and Rtn). Regarding claim 7, the combined device shows wherein the halogen element is located at an interface between the channel layer and the silicide layer (see Fig. 5, concentration at interface of Rch and Rco; modified by Jang to include silicide at interface between channel and core). Regarding claim 8, Isogai further discloses a tunneling layer (21, see [0035]) surrounding the channel layer; a data storage layer (22, see [0035]) surrounding the tunneling layer; and a blocking layer (23, see [0035]) surrounding the data storage layer, wherein at least one of the tunneling layer, the data storage layer, and the blocking layer includes the halogen element (see Fig. 5). Regarding claim 9, Isogai further discloses wherein the tunneling layer includes the halogen element at a third concentration, and an interface between the tunneling layer and the channel layer includes the halogen element at a second concentration higher than the third concentration (e.g. concentration in Rt1 compared to at interface between Rtn and Rch, see Fig. 5). Regarding claim 10, the combined device shows an insulating core located in the silicide layer (Jang: 134a/134b, see [0075]). Regarding claim 12, Isogai discloses the invention as applied to claim 11 above, but does not explicitly disclose a silicide layer located between the channel layer and the insulating core. Jang teaches the limitation in the same manner and for the same reasons as applied to claim 1 above. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20210249420 and US 20190371814 are each cited for showing memory device with halogen element dopants. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896 12/22/2025
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Prosecution Timeline

Apr 26, 2023
Application Filed
Dec 02, 2025
Response Filed
Dec 22, 2025
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
40%
Grant Probability
70%
With Interview (+30.7%)
3y 7m
Median Time to Grant
Low
PTA Risk
Based on 375 resolved cases by this examiner. Grant probability derived from career allow rate.

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