DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/04/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 05-04-2026 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10, 12-15, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, and 8 of U.S. Patent No. US12402426B2. Although the claims at issue are not identical, they are not patentably distinct from each other. Listed below are the claim limitations of US patent US12402426B2 that correspond to the claim limitations recited in the instant application:
“a first well having a first conductivity type;
a second well provided on the first well and having a second conductivity type that is different from the first conductivity type;
the first contact region has the first conductivity type;
further comprising a guard ring region provided on a side surface of the second well, wherein the guard ring region has the second conductivity type.”
Claims 1-10, 12-15, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1- 20 of U.S. copending application 18/308,202. Although the claims at issue are not identical, they are not patentably distinct from each other. Listed below are the claim limitations of US18308,202 application that correspond to the claim limitations recited in the instant application.
“ a first well having a first conductivity type;
a second well provided on the first well and having the first conductivity type;
a heavily doped region provided on the second well and having a second
conductivity type different from the first conductivity type;
a contact having the first conductivity type;
wherein the guard ring extends to a side surface of the second well.
wherein a bottom surface of the guard ring is located at a depth between a bottom surface and an upper surface of the second well.
wherein a bottom surface of the guard ring is located at the same depth as a bottom surface of the second well.
wherein a bottom surface of the second well is located at a depth between an upper surface and a bottom surface of the guard ring.
further comprising an isolation region provided on the opposite side of the guard ring with the contact interposed therebetween
wherein the heavily doped region protrudes from a side of the second well.
wherein a side of the heavily doped region and a side of the second well forms a coplanar.
wherein the first well is located in a region between the relief region and the
guard ring.
A LiDAR device comprising an electronic device: wherein the electronic device includes a single photon detection element,
a contact provided on an opposite side of the heavily doped region with respect to the guard ring
wherein a bottom surface of the contact is in contact with the relief region.”
Claims 1-10, 12-15, 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1- 20 of U.S. copending application 18731151. Although the claims at issue are not identical, they are not patentably distinct from each other. Listed below are the claim limitations of US18731151 application that correspond to the claim limitations recited in the instant application.
“a contact provided on an opposite side of the heavily doped region
a first well provided on the bottom surface of the heavily doped region and having the first conductivity type
a second well provided between the heavily doped region and the first well and having the first conductivity type,
wherein a side surface of the heavily doped region and a side surface of the second well are vertically aligned.
a relief region having the first conductivity type
a first well provided on the bottom surface of the heavily doped region and having the first conductivity type, wherein the first well extends between the guard ring and the relaxation region. “
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Objections
Claims 11 and 12 are objected to because of the following informalities:
Claim 11 recites “a contact provided on the opposite side of the heavily doped region”; this may be written as “a contact provided on the outer side of the heavily doped region” or “a contact provided peripheral to the heavily doped region”
Claim 12 recites “an isolation region provided on the opposite side of the guard ring”; this may be written as “an isolation region provided on the outer side of the guard ring” or “an isolation region provided peripheral to the guard ring”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5, 8 - 9, 12-14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Bose et al. (IEEE Sensors Journal, “Parametric Study of p-n Junctions and Structures for CMOS-Integrated Single-Photon Avalanche Diodes”; hereinafter Bose) in view of Webster et al. (US20130193546A1; hereinafter Webster).
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[AltContent: textbox (Heavily doped region: p+)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Insulation pattern: STI)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Contact: N)][AltContent: arrow][AltContent: arrow][AltContent: textbox (First well: DNW)][AltContent: textbox (Second well: NW)][AltContent: textbox (Guard Ring: PWELL)][AltContent: textbox (Isolation Region: STI)]
Annotated by Examiner - Bose: FIG. 1(a)
Regarding Claim 1 (Amended), Bose discloses a single photon detection device (Bose: FIG. 1(a) reproduced above and annotated by examiner, Page 5292, Section IIA, single photon avalanche diode) comprising:
a first well (deep-n-well (DNW), FIG. 1(a), Page 5292, Section IIA;
a heavily doped region provided on the first well (p+ region), FIG. 1(a), Page 5292, Section IIA,B. Bose discloses the heavily doped p+ region is provided on the n-well (NW) which is formed on the first well (DNW).
a guard ring (PWELL) provided on a side surface of the heavily doped region (p+), FIG. 1(a), Page 5292, Section IIB. Bose discloses the p+/n-well junction is surrounded by lightly-doped p-well guard ring.
an insulating pattern (shallow trench isolation STI) inserted into the guard ring (PWELL). FIG. 1(a), Page 5292, Section IIA.
a contact (n+ region N) provided on the opposite side of the heavily doped region (p+ region) with the guard ring (PWELL) interposed therebetween, FIG. 1(a), Page 5292, Section IIA; and
a relief region (p-substrate) surrounding the guard ring (PWELL) and being spaced apart from the guard ring (DNW between them), FIG. 1(a), Page 5292, Section IIA.
Bose discloses junctions formed using lightly doped layers such as p-well/deep n-well or n+/p-substrate have demonstrated to reduce noise. Therefore, the p-substrate is interpreted as a relief region.
wherein the first well (DNW) has a first conductivity type, FIG. 1(a), Page 5292, Section IIA. Bose discloses the first well (DNW) is n-type which is the first conductivity type;
wherein the heavily doped region (p+ region) and the guard ring (PWELL) have a second conductivity type (p-type) different from the first conductivity type (n-type), FIG. 1(a), Page 5292, Section IIB.
Bose discloses the heavily doped region (p+ region) and the guard ring (PWELL) have a second conductivity type which is p-type; different from the first conductivity type which is n-type.
wherein the contact (n+ region N) has the first conductivity type (the contact has the first conductivity type which is n type), FIG. 1(a), Page 5292, Section IIA; and
wherein a portion of the first well (DNW) is disposed between the relief region (p-substrate) and the guard ring (PWELL), FIG. 1(a), Page 5292, Section IIA.
Bose does not disclose “wherein the relief region directly contacts side surfaces and a bottom surface of the contact.”
In a similar art, Webster discloses a single photon avalanche diode, SPAD, FIG. 8, [0115].
Webster discloses: wherein the relief region (N-WELL) directly contacts side surfaces and a bottom surface of the contact (heavily doped n+ region connected to cathode contacts), FIG. 8, [0116].
Webster [0102] discloses the wells and associated electrode implants provides a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated. Therefore, the well region is interpreted as the relief region.
Webster discloses that a photodiode as taught provides a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated [0102]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Bose’s device in order to provide a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated as disclosed by Webster [0102].
Regarding Claim 2 (Original), The combination of Bose and Webster discloses the single photon detection device of claim 1.
Bose discloses: wherein the insulating pattern (STI) is apart from the heavily doped region (p+ region) by the guard ring (PWELL), FIG.1(a), Page 5292, Section IIB.
Regarding Claim 3 (Original), The combination of Bose and Webster discloses the single photon detection device of claim 1.
Bose discloses: wherein the guard ring (PWELL) is in contact with the heavily doped region (p+), FIG.1(a), Page 5292, Section IIB. Bose discloses the p+/n-well junction is surrounded by lightly-doped P-well guard ring indicating the guard ring is in contact with the heavily doped region.
Regarding Claim 4 (Original), The combination of Bose and Webster discloses the single photon detection device of claim 1.
Bose discloses: further comprising: a second well (n-well NW) provided between the first well (DNW) and the heavily doped region (p+ region),
wherein the second well (NW) has the first conductivity type (second well NW is n-type which is the first conductivity type). FIG.1(a), Page 5292, Section IIB.
Regarding Claim 5 (Original), The combination of Bose and Webster discloses the single photon detection device of claim 4.
Bose discloses: wherein the guard ring (PWELL) extends to a side surface of the second well (NW), FIG.1(a), Page 5292, Section IIB. Bose discloses the second well (NW) is surrounded by lightly-doped p-well guard ring (Bose: PWELL), which indicates the guard ring extends to a side surface of the second well.
Regarding Claim 8 (Previously Presented), The combination of Bose and Webster discloses the single photon detection device of claim 4.
Bose does not disclose “wherein a bottom surface of the second well is located at a depth between a top surface and a bottom surface of the guard ring.”
Webster discloses a single photon avalanche diode (Webster: Fig.11 reproduced below, fourth variant of the single photon avalanche diode): wherein a bottom surface of the second well (N-WELL) is located at a depth between a top surface and a bottom surface of the guard ring (Reduced P-Doping Guard Ring), FIG. 11. [0123].
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Webster: FIG. 11
Webster discloses that a photodiode with the guard ring construction as taught achieves a desired increase in peripheral breakdown voltage and thus permits effective Geiger mode operation [0128]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to achieve a desired increase in peripheral breakdown voltage and thus permit effective Geiger mode operation as disclosed by Webster [0128].
Regarding Claim 9 (Original), The combination of Bose and Webster disclose the single photon detection device of claim 4.
Bose discloses: wherein the heavily doped region (p+ region) protrudes from a side surface of the second well (NW), FIG. 1(a), Page 5292, Section IIB. Bose discloses the p+ implant is extended beyond the underlying n-well to connect it to the p-well guard ring, which indicates the heavily doped p+ region protrudes from a side surface of the second well NW.
Regarding Claim 12 (Currently Amended), The combination of Bose and Webster discloses the single photon detection device of claim 1.
Bose discloses: further comprising: an isolation region (isolation region: STI) provided on the opposite side of the guard ring (PWELL) with the contact (n+ region N) interposed therebetween. The annotated FIG. 1(a) shows the single photon detection device comprises an isolation region (Isolation region: STI) provided on the opposite side of the guard ring (PWELL) and the contact (n+ region N) is interposed between them.
Regarding Claim 13, Bose discloses an electronic device (SPAD test array implemented in CMOS process, Abstract, Page 5291) comprising:
a single photon detection device (single photon avalanche diode) including a first well (deep-n-well (DNW)), FIG. 1(a), Page 5292, Section IIA;
a heavily doped region provided on the first well (p+ region), FIG. 1(a), Page 5292, Section IIA,B. Bose discloses the heavily doped p+ region is provided on the n-well (NW) which is formed on the first well (DNW).
a guard ring (PWELL) provided on a side surface of the heavily doped region (p+), FIG. 1(a), Page 5292, Section IIB. Bose discloses the p+/n-well junction is surrounded by lightly-doped p-well guard ring.
an insulating pattern (shallow trench isolation STI) inserted into the guard ring (PWELL). FIG. 1(a), Page 5292, Section IIA.
a contact (n+ region N) provided on the opposite side of the heavily doped region (p+ region) with the guard ring (PWELL) interposed therebetween, FIG. 1(a), Page 5292, Section IIA; and
a relief region (p-substrate) surrounding the guard ring (PWELL) and being spaced apart from the guard ring (DNW between them), FIG. 1(a), Page 5292, Section IIA.
Bose discloses junctions formed using lightly doped layers such as p-well/deep n-well or n+/p-substrate have demonstrated to reduce noise. Therefore, the p-substrate is interpreted as a relief region.
wherein the first well (DNW) has a first conductivity type, FIG. 1(a), Page 5292, Section IIA. Bose discloses the first well (DNW) is n-type which is the first conductivity type;
wherein the guard ring (PWELL) covers side surfaces and a bottom surface of the insulating pattern (STI) so that a top surface of the insulating pattern (STI) is exposed, FIG. 1(a), FIG. 1(a), Page 5292, Section IIB.
the heavily doped region (p+ region) and the guard ring (PWELL) have a second conductivity type (p-type) different from the first conductivity type (n-type), FIG. 1(a), Page 5292, Section IIB.
Bose discloses the heavily doped region (p+ region) and the guard ring (PWELL) have a second conductivity type which is p-type; different from the first conductivity type which is n-type.
wherein the contact (n+ region N) has the first conductivity type (the contact has the first conductivity type which is n type), FIG. 1(a), Page 5292, Section IIA; and
wherein a portion of the first well (DNW) is disposed between the relief region (p-substrate) and the guard ring (PWELL), FIG. 1(a), Page 5292, Section IIA.
Bose does not disclose “wherein the relief region directly contacts side surfaces and a bottom surface of the contact.”
In a similar art, Webster discloses a single photon avalanche diode, SPAD, FIG. 8, [0115].
Webster discloses: wherein the relief region (N-WELL) directly contacts side surfaces and a bottom surface of the contact (heavily doped n+ region connected to cathode contacts), FIG. 8, [0116].
Webster [0102] discloses the wells and associated electrode implants provides a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated. Therefore, the well region is interpreted as the relief region.
Webster discloses that a photodiode as taught provides a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated [0102]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Bose’s device in order to provide a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated as disclosed by Webster [0102].
Regarding Amended Claim 14, Bose discloses a LiDAR device (CMOS-integrated SPAD for time-resolved and time-of-flight optical detection, Conclusion, Page 5297) comprising:
an electronic device including a single photon detection device (SPAD test array implemented in CMOS process, Abstract, Page 5291)
wherein the single photon detection device (SPAD) includes
a first well (deep-n-well (DNW), FIG. 1(a), Page 5292, Section IIA;
a heavily doped region provided on the first well (p+ region), FIG. 1(a), Page 5292, Section IIA,B. Bose discloses the heavily doped p+ region is provided on the n-well (NW) which is formed on the first well (DNW).
a guard ring (PWELL) provided on a side surface of the heavily doped region (p+), FIG. 1(a), Page 5292, Section IIB. Bose discloses the p+/n-well junction is surrounded by lightly-doped p-well guard ring.
an insulating pattern (shallow trench isolation STI) inserted into the guard ring (PWELL). FIG. 1(a), Page 5292, Section IIA.
a contact (n+ region N) provided on the opposite side of the heavily doped region (p+ region) with the guard ring (PWELL) interposed therebetween, FIG. 1(a), Page 5292, Section IIA; and
a relief region (p-substrate) surrounding the guard ring (PWELL) and being spaced apart from the guard ring (DNW between them), FIG. 1(a), Page 5292, Section IIA.
Bose discloses junctions formed using lightly doped layers such as p-well/deep n-well or n+/p-substrate have demonstrated to reduce noise. Therefore, the p-substrate is interpreted as a relief region.
wherein the first well (DNW) has a first conductivity type, FIG. 1(a), Page 5292, Section IIA. Bose discloses the first well (DNW) is n-type which is the first conductivity type;
wherein the guard ring (PWELL) covers side surfaces and a bottom surface of the insulating pattern (STI) so that a top surface of the insulating pattern (STI) is exposed, FIG. 1(a), FIG. 1(a), Page 5292, Section IIB.
wherein the heavily doped region (p+ region) and the guard ring (PWELL) have a second conductivity type (p-type) different from the first conductivity type (n-type), FIG. 1(a), Page 5292, Section IIB.
Bose discloses the heavily doped region (p+ region) and the guard ring (PWELL) have a second conductivity type which is p-type; different from the first conductivity type which is n-type.
wherein the contact (n+ region N) has the first conductivity type (the contact has the first conductivity type which is n type), FIG. 1(a), Page 5292, Section IIA; and
wherein a portion of the first well (DNW) is disposed between the relief region (p-substrate) and the guard ring (PWELL), FIG. 1(a), Page 5292, Section IIA.
Bose does not disclose “wherein the relief region directly contacts side surfaces and a bottom surface of the contact.”
In a similar art, Webster discloses a single photon avalanche diode, SPAD, FIG. 8, [0115].
Webster discloses: wherein the relief region (N-WELL) directly contacts side surfaces and a bottom surface of the contact (heavily doped n+ region connected to cathode contacts), FIG. 8, [0116].
Webster [0102] discloses the wells and associated electrode implants provides a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated. Therefore, the well region is interpreted as the relief region.
Webster discloses that a photodiode as taught provides a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated [0102]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Bose’s device in order to provide a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated as disclosed by Webster [0102].
Regarding Claim 17 (Currently Amended), The combination of Bose and Webster discloses the single photon detection device of claim 1.
Bose does not disclose “wherein the relief region has the first conductivity type with a doping concentration higher than that of the first well.”
Webster discloses: wherein the relief region (N-WELL) has the first conductivity type (n type) with a doping concentration higher than that of the first well (N-type epitaxial layer), FIG. 8, [0116].
Webster [0116] discloses the formation of the n-well within the n-type epitaxial layer. It would have been obvious to one of ordinary skill in the art that the implanted n-well has a higher doping concentration that the n-type epitaxial layer it is formed within.
Webster discloses that a photodiode as taught provides a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated [0102]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to provide a uniform and low resistance circuit path for the avalanche current to discharge when the SPAD is activated as disclosed by Webster [0102].
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Bose in view of Webster, further in view of Cheng et al. (CN110767767A; hereinafter Cheng).
Regarding Claim 6 (Previously presented), The combination of Bose and Webster discloses the single photon detection device of claim 4.
The combination of Bose and Webster does not disclose “wherein a bottom surface of the guard ring located at a depth between a bottom surface and a top surface of the second well.”
In a similar art, Cheng discloses a novel SPAD detector [0019].
Cheng discloses: wherein a bottom surface of the guard ring (Pwell) located at a depth between a bottom surface and a top surface of the second well (n-type), FIG. 1 reproduced below, [0019].
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Cheng: FIG. 1
Cheng discloses that a device as taught effectively reduces the edge electric field of the reactive junction, thereby reducing the dark count of the SPAD detector [0013]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Bose and Webster’s device to effectively reduce the edge electric field of the reactive junction, thereby reducing the dark count of the SPAD detector [0013].
Regarding Claim 7 (Original), The combination of Bose and Webster discloses the single photon detection device of claim 4.
The combination of Bose and Webster does not disclose “wherein the second well extends onto the bottom surface of the guard ring.”
Cheng discloses: wherein the second well (n-type) extends onto the bottom surface of the guard ring (Pwell), FIG. 1, [0019].
Cheng FIG.1, [0019] discloses the second well (n-type) lies below the heavily doped p+ region (P+) and its surrounding guard ring (Pwell), indicating that the second well extends onto the bottom surface of the guard ring.
Cheng discloses that a device as taught effectively reduces the edge electric field of the reactive junction, thereby reducing the dark count of the SPAD detector [0013]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Bose and Webster’s device to effectively reduce the edge electric field of the reactive junction, thereby reducing the dark count of the SPAD detector [0013].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Bose in view of Webster, further in view of Rhim et al. (IEEE, “Guard-ring dependence of noise characteristics for single-photon avalanche diodes in a standard CMOS technology”; hereinafter Rhim).
Regarding Claim 10 (Original), The combination of Bose and Webster discloses the single photon detection device of claim 4.
The combination of Bose and Webster does not disclose “wherein a side surface of the heavily doped region and a side surface of the second well directly adjacent to the side surface of the heavily doped region form a coplanar surface.”
In a similar art, Rhim discloses the effects of guard-ring structure on noise characteristics for CMOS-compatible single photon avalanche diodes [Abstract, Page 155].
Rhim discloses: wherein a side surface of the heavily doped region (P+ region) and a side surface of the second well (N-well) directly adjacent to the side surface of the heavily doped region form a coplanar surface. [FIG 2(a) reproduced below, Page 156, Paragraph 1].
Rhim [FIG 2(a), Page 156, Paragraph 1] discloses a single photon avalanche diode configuration in which the heavily doped P+ region extends laterally to align with the side surface of the N-well, indicating the side surface of the P+ region and N-well are coplanar.
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Rhim: FIG. 2(a)
Rhim discloses that a device as taught improves performance by suppressing lateral tunning [Page 156, Paragraph 2]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Bose and Webster’s device to improve the performance by suppressing lateral tunning [Page 156, Paragraph 2].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Bose in view of Webster, further in view of Augusto et al. (US20070290265A1; hereinafter Augusto).
Regarding Claim 15 (Previously Presented), The combination of Bose and Webster discloses the single photon detection device of claim 1.
The combination of Bose and Webster does not disclose “wherein the guard ring entirely covers a bottom surface of the insulating pattern.”
In a similar art, Augusto discloses monolithic integration of epitaxial device layers with CMOS devices [0002].
Augusto discloses: wherein the guard ring (119) entirely covers a bottom surface of the insulating pattern (102), FIG. 6, [0032].
Augusto discloses that a device as taught reduces edge breakdown and improves the manufacturability and performance of the fabricated device [0004], [0133]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Bose and Webster’s device in order to reduce edge breakdown and improve the manufacturability and performance of the fabricated device as disclosed by Augusto [0004], [0133].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KRISHNA PALANISWAMY whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights