DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Species I directed to Fig. 3A (claims 1-8, 11, 13-16 and 19-20) in the reply filed on August 28th, 2025 is acknowledged.
Claims 9-10, 12, 17-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Claim Objections
Claims 1-5, 19 and 20 are objected to because of the following informalities:
Claim 1 recites “the first circuit area” in line 10 which refers back to “a first circuit area of the plurality of circuit areas” in line 6 and should be amended to “the first circuit area of the plurality of circuit areas” for avoiding confusion. Appropriate correction is required.
Claim 2 recites “the first circuit area” in line 2 which refers back to “a first circuit area of the plurality of circuit areas” in line 6 of claim 1 and should be amended to “the first circuit area of the plurality of circuit areas” for avoiding confusion. Appropriate correction is required.
Claim 3 recites “the first circuit area” in line 6 which refers back to “a first circuit area of the plurality of circuit areas” in line 6 of claim 1 and should be amended to “the first circuit area of the plurality of circuit areas” for avoiding confusion. Appropriate correction is required.
Claim 4 recites “the first circuit area” in line 3 which refers back to “a first circuit area of the plurality of circuit areas” in line 6 of claim 1 and should be amended to “the first circuit area of the plurality of circuit areas” for avoiding confusion. Appropriate correction is required.
Claim 5 recites “the first circuit area” in line 5 which refers back to “a first circuit area of the plurality of circuit areas” in line 6 of claim 1 and should be amended to “the first circuit area of the plurality of circuit areas” for avoiding confusion. Appropriate correction is required.
Claim 19 recites “the first circuit area” in line 14 which refers back to “a first circuit area of the plurality of circuit areas” in line 10 and should be amended to “the first circuit area of the plurality of circuit areas” for avoiding confusion. Appropriate correction is required.
Claim 20 recites “the first circuit area” in line 5 which refers back to “a first circuit area of the plurality of circuit areas” in line 10 of claim 19 and should be amended to “the first circuit area of the plurality of circuit areas” for avoiding confusion. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 3 recites the limitation “the first horizontal direction” in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites “second circuit area” in line 6 and “third circuit area” in line 9. However, claims 11 and 13 fails to recite “first circuit area”. It is unclear to the examiner how can the second circuit area and third circuit area be provided without having the first circuit area.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (Pub. No.: US 2020/0066742 A1), hereinafter as Kim.
Regarding claim 1, Kim discloses a semiconductor device in Figs. 3-6 comprising: a peripheral circuit structure (peripheral circuit structure PRS) including a plurality of circuit areas (plurality of transistor TR) (see Fig. 5 and [0047]); a cell array structure (ST1, ST2 and SRS1) including a pair of memory cell blocks (stacks ST1 and ST2) overlapping the peripheral circuit structure in a first direction (Z direction) and spaced apart in a second direction (X direction), perpendicular to the first direction, with a peripheral circuit connection area (separation structure SRS1) therebetween (see Fig. 5 and [0039], [0046], [0049-0050]); a first circuit area of the plurality of circuit areas (transistors TR in peripheral region PR1) that overlaps the peripheral circuit connection area in the first direction (see Fig. 5 and [0048]); and at least one contact plug (contact plug PCP1) extending in the first direction from the peripheral circuit connection area, and including a first end portion (lower end portion of contact plug PCP1) configured to connect to at least one circuit (a transistor TR in peripheral region PR1) included in the first circuit area and facing the first circuit area and a second end portion (upper end portion of contact plug PCP1) configured to connect to an external connection terminal (interconnection line ICN) (see Fig. 5 and [0073-0074]).
Regarding claim 4, Kim discloses the semiconductor device of claim 1, wherein the peripheral circuit structure and the pair of memory cell blocks are included in one chip (PRS and stacks ST1/ST2/MRS1 are packaged together into one structure in Fig. 5), wherein the first circuit area and the peripheral circuit connection area each extend along a third direction (Y direction) orthogonal to the second direction, from a center area (an area between blocks BLK1 and BLK2 can be a center area of two blocks) in the second direction of the one chip (see Figs. 3-5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (Pub. No.: US 2020/0066742 A1), hereinafter as Kim as applied to claim 1 above, and further in view of SHIN et al. (Pub. No.: US 2015/0129878 A1), hereinafter as Shin.
Regarding claim 2, Kim discloses the semiconductor device of claim 1, but
fails to disclose wherein the at least one circuit included in the first circuit area comprises a data input/ouput circuit.
Shin discloses a semiconductor device in Figs. 1A-1B comprising: a peripheral circuit structure (peripheral circuit in peripheral regions II) including a plurality of circuit area (plurality of transistors 120 ) (see Fig. 1B and [0044-0045]); a first circuit area of the plurality of circuit area overlaps a peripheral circuit connection area (area having interconnection structure 230) in a first direction (Z direction) (see Fig. 1B and [0072-0073]); wherein at least one circuit (transistor 120 connecting to interconnection structure 230) included in a first circuit area (peripheral region II) comprises a data input/ouput circuit (peripheral circuits in peripheral region II process data input/output from memory cell array region I) (see Fig. 1B and [0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the at least one circuit in the first circuit area of semiconductor device of Kim to include data input/output circuit as same as the semiconductor device of Shin because the modified structure would improve the overall performance of the memory device by optimizing circuit design with low power loss and faster transfer rates since everything compacts in one circuit designs, furthermore the modified structure would also reduce manufacturing cost for having higher density circuit.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (Pub. No.: US 2020/0066742 A1), hereinafter as Kim, as applied to claim 1 above and in view of MIZUTANI et al. (Pub. No.: US 2021/0035965 A1), hereinafter as Mizutani.
Regarding claim 5, Kim discloses the semiconductor device of claim 1, but
fails to disclose wherein the cell array structure further comprises a first bonding metal pad, wherein the peripheral circuit structure further comprises a second bonding metal pad, wherein the at least one contact plug is configured to connect to the at least one circuit included in the first circuit area through a bonding structure including the first bonding metal pad and the second bonding metal pad.
Mizutani discloses a semiconductor device in Fig. 21 comprising an cell array structure (array of memory elements in memory die 1000) and a peripheral circuit structure (logic die 700) (see [0115]), and wherein the cell array structure further comprises a first bonding metal pad (first bonding structure 178) (see [0115] and [0120]), wherein the peripheral circuit structure further comprises a second bonding metal pad (second bonding structure 788) (see [0118-0120]), wherein the at least one contact plug (a contact via structure 8P) is configured to connect to at least one circuit (transistor having active region 742) included in the first circuit area of the peripheral circuit through a bonding structure (combination of first and second bonding structures 178 and 788) including the first bonding metal pad and the second bonding metal pad (see [0111-0113]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the bonding structure including the first and second bonding pads of Mizutani into the semiconductor device of Kim because the modified structure would provide a reliable bonding structure by memory region and peripheral region and further reduce noise and crosstalk from the peripheral circuit into the memory region.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (Pub. No.: US 2020/0066742 A1), hereinafter as Kim in view of SHIN et al. (Pub. No.: US 2015/0129878 A1), hereinafter as Shin.
Regarding claim 11, Kim discloses a semiconductor device in Figs. 3-6 comprising: a peripheral circuit structure (peripheral circuit structure PRS) (see Fig. 5 and [0047]); and a cell array structure (ST1, ST2 and SRS1) overlapping the peripheral circuit structure in a first direction (Z direction), wherein the peripheral circuit structure comprises a circuit area (peripheral region PR1) extending, from a center area (an area between blocks BLK1 and BLK2 can be considered as a center area of two blocks) in a second direction (X direction) of the peripheral circuit structure, along a third direction (Z direction) orthogonal to the second direction, the first direction being orthogonal to the first and second directions, wherein the cell array structure comprises: a peripheral circuit connection area (separation structure SRS1) overlapping the circuit area in the first direction (see Figs. 3-5 and [0039], [0046], [0049-0050]); a first memory cell block (stack ST1) and a second memory cell block (stack ST2) spaced apart in the second direction with the peripheral circuit connection area therebetween (see Fig. 5 and [0048-0050]); and a plurality of contact plugs (plurality of contact plugs PCP1) extending in the first direction from the peripheral circuit connection area, and each including a first end portion (lower end portion of contact plug PCP1) configured to connect to at least one circuit included in the circuit area (transistors TR in peripheral region PR1) and facing the circuit area and a second end portion (upper end portion of contact plug PCP1) configured to connect to an external connection terminal (interconnection line ICN) (see Fig. 5 and [0073-0074]).
Kim fails to disclose the peripheral circuit structure comprises the circuit area being a data input/output circuit area.
Shin discloses a semiconductor device in Figs. 1A-1B comprising: a peripheral circuit structure (peripheral circuit in peripheral regions II) comprising a data input/ouput circuit area (peripheral region II) (see Fig. 1B and [0041], [0044-0045]); a peripheral circuit connection area (area having interconnection structure 230) overlapping the data input/output circuit area in a first direction (Z direction) (see Fig. 1B and [0072-0073]); wherein at least one circuit (transistor 120 connecting to interconnection structure 230) included in data input/output circuit area (peripheral region II) (peripheral circuits in peripheral region II process data input/output from memory cell array region I) (see Fig. 1B and [0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the circuit area in the peripheral circuit structure of semiconductor device of Kim to include data input/output circuit area as same as the semiconductor device of Shin because the modified structure would improve the overall performance of the memory device by optimizing circuit design with low power loss and faster transfer rates since everything compacts in one circuit designs, furthermore the modified structure would also reduce manufacturing cost for having higher density.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (Pub. No.: US 2020/0066742 A1), hereinafter as Kim in view of SHIN et al. (Pub. No.: US 2015/0129878 A1), hereinafter as Shin, as applied to claim 11 and further in view of MIZUTANI et al. (Pub. No.: US 2021/0035965 A1), hereinafter as Mizutani.
Regarding claim 14, Kim discloses the semiconductor device of claim 11, but
fails to disclose wherein the cell array structure further comprises a plurality of first bonding metal pads, wherein the peripheral circuit structure further comprises a plurality of second bonding metal pads constituting a plurality of bonding structures together with the plurality of first bonding metal pads, wherein the plurality of contact plugs are configured to connect to the at least one circuit included in the data input/output circuit area through one bonding structure of the plurality of bonding structures.
Mizutani discloses a semiconductor device in Fig. 21 comprising an cell array structure (array of memory elements in memory die 1000) and a peripheral circuit structure (logic die 700) (see [0115]), and wherein the cell array structure further comprises a plurality of first bonding metal pads (plurality of first bonding structures 178) (see [0115] and [0120]), wherein the peripheral circuit structure further comprises a plurality of second bonding metal pads (plurality of second bonding structures 788) constituting a plurality of bonding structures together with the plurality of first bonding metal pads (see [0118-0120]), wherein the plurality of contact plugs (a plurality of contact via structure 8P) are configured to connect to the at least one circuit included in the data input/output circuit area through one bonding structure of the plurality of bonding structures (see [0111-0113]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the bonding structure including a plurality of the first and second bonding pads of Mizutani into the semiconductor device of Kim because the modified structure would provide a reliable bonding structure by memory region and peripheral region and further reduce noise and crosstalk from the peripheral circuit into the memory region.
Claim 19-20 is rejected under 35 U.S.C. 103 as being unpatentable over SEO et al. (Pub. No.: US 2019/0373730 A1), hereinafter as Seo in view of KIM et al. (Pub. No.: US 2020/0066742 A1), hereinafter as Kim.
Regarding claim 19, Seo discloses an electronic system in Figs. 5A-5B comprising: a main board (PCB 10) (see [0048-0049]); a semiconductor device (semiconductor package 120) on the main board (see Fig. 5B, [0024-0025], [0073-0074]); and a controller (memory controller 140) electrically connected to the semiconductor device on the main board, wherein the semiconductor device comprises a 3D memory array (see Fig. 5A-5B and [0075], [0079-0081]).
Seo fails to disclose the semiconductor device comprises: a peripheral circuit structure including a plurality of circuit areas; a cell array structure including a pair of memory cell blocks overlapping the peripheral circuit structure in a first direction and spaced apart in a second direction, perpendicular to the first direction, with a peripheral circuit connection area therebetween; a first circuit area of the plurality of circuit areas that overlaps the peripheral circuit connection area in the first direction; and at least one contact plug extending in the first direction from the peripheral circuit connection area, and including: a first end portion configured to connect to at least one circuit included in the first circuit area and facing the first circuit area; and a second end portion configured to connect to an external connection terminal.
Kim discloses a semiconductor device in Figs. 3-6 comprising: a peripheral circuit structure (peripheral circuit structure PRS) including a plurality of circuit areas (plurality of transistor TR) (see Fig. 5 and [0047]); a cell array structure (ST1, ST2 and SRS1) including a pair of memory cell blocks (stacks ST1 and ST2) overlapping the peripheral circuit structure in a first direction (Z direction) and spaced apart in a second direction (X direction), perpendicular to the first direction, with a peripheral circuit connection area (separation structure SRS1) therebetween (see Fig. 5 and [0039], [0046], [0049]); a first circuit area of the plurality of circuit areas (transistors TR in peripheral region PR1) that overlaps the peripheral circuit connection area in the first direction (see Fig. 5 and [0048]); and at least one contact plug (contact plug PCP1) extending in the first direction from the peripheral circuit connection area, and including a first end portion (lower end portion of contact plug PCP1) configured to connect to at least one circuit (a transistor TR in peripheral region PR1) included in the first circuit area and facing the first circuit area and a second end portion (upper end portion of contact plug PCP1) configured to connect to an external connection terminal (interconnection line ICN) (see Fig. 5 and [0073-0074]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Seo to have the same structure as the semiconductor device of Kim being described above because the modified structure would provide high performance and reliable memory device at the same time with reduced chip size for lowering manufacturing cost.
Regarding claim 20, the combination of Seo and Kim discloses the semiconductor device of claim 19, wherein the main board further comprises wiring patterns (channels CH1-CH4) electrically connecting the semiconductor device and the controller to each other (see Seo, Fig. 5A and [0073]), wherein, in the semiconductor device, the peripheral circuit structure and the pair of memory cell blocks are included in one chip (PRS and stacks ST1/ST2/MRS1 are packaged together into one structure in Fig. 5 of Kim), wherein the first circuit area and the peripheral circuit connection area each extend along a third direction (Y direction) orthogonal to the second direction, from a center area (an area between blocks BLK1 and BLK2 can be a center area of two blocks) in the second direction of the one chip (see Figs. 3-5 of Kim).
Allowable Subject Matter
Claims 3 and 13 would be objected to as being dependent upon a rejected base claim, but would be allowable if amend to overcome 112 rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6-8 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: the prior art made of record does not teach or fairly suggest the following: wherein each of the pair of memory cell blocks comprises:
A memory cell area including a plurality of gate lines sequentially stacked along the first direction, and a connection area including a plurality of conductive pad areas integrally connected to the plurality of gate lines, wherein the plurality of circuit areas further comprise: a second circuit area adjacent to the first circuit area in the second direction, and a third circuit area adjacent to the second circuit area in the second direction and spaced apart from the first circuit area in the first horizontal direction with the second circuit area therebetween, wherein the second circuit area and the third circuit area overlap the connection area of one memory cell block of the pair of memory cell blocks in the first direction, wherein a first one of the second circuit area and the third circuit area comprises a row decoder area, and a second one of the second circuit area and the third circuit area comprises a pass circuit area including a plurality of pass transistors as recited in claim 3.
A memory cell area including a plurality of gate lines sequentially stacked along the first direction, and a connection area including a plurality of conductive pad areas integrally connected to the plurality of gate lines, wherein the plurality of conductive pad areas of each of the pair of memory cell blocks decrease in planar area with decreasing distance from the peripheral circuit structure, such that a limited cell connection area is formed between the peripheral circuit structure and the plurality of conductive pad areas, wherein, in each of the pair of memory cell blocks, the memory cell area is spaced apart from the peripheral circuit connection area with the cell connection area therebetween as in claim 6.
Further comprising a pair of common source lines spaced apart from the peripheral circuit structure in the first direction with a memory cell area of each of the pair of memory cell blocks therebetween and spaced apart in the second direction with the peripheral circuit connection area therebetween, and at least one connection pad between the pair of common source lines in the peripheral circuit connection area and connected to the second end portion of the at least one contact plug as recited in claim 7.
Wherein each of the pair of memory cell blocks comprises: a memory cell area including a plurality of gate lines sequentially stacked along the first direction, and a connection area including a plurality of conductive pad areas integrally connected to the plurality of gate lines, wherein the plurality of circuit areas further comprise a second circuit area on a same level in the first direction as the first circuit area and overlapping the connection area in the first direction, wherein the cell array structure further comprises a plurality of first bonding metal pads, wherein the peripheral circuit structure further comprises a plurality of second bonding metal pads, wherein the at least one contact plug is configured to connect to the at least one circuit included in the first circuit area through a first bonding structure including a first bonding metal pad of the plurality of first bonding metal pads and a first bonding metal pad of the plurality of second bonding metal pads, wherein each of the plurality of gate lines is configured to connect to a circuit in the second circuit area through a second bonding structure including a second bonding metal pad of the plurality of first bonding metal pads and a second bonding metal pad of the plurality of second bonding metal pads as recited in claim 8.
wherein each of the first memory cell block and the second memory cell block comprises: a memory cell area including a plurality of gate lines sequentially stacked in the first direction, and a connection area including a plurality of conductive pad areas integrally connected to the plurality of gate lines, wherein the peripheral circuit structure further comprises: a pair of second circuit areas spaced apart in the second direction with the data input/output circuit area therebetween and overlapping connection areas of each of the first memory cell block and the second memory cell block in the first direction; a pair of third circuit areas spaced apart in the second direction with the data input/output circuit area and the pair of second circuit areas therebetween and overlapping connection areas of each of the first memory cell block and the second memory cell block in the first direction; and a pair of fourth circuit areas spaced apart in the second direction with the data input/output circuit area, the pair of second circuit areas, and the pair of third circuit areas therebetween and overlapping each of the memory cell areas of the first memory cell block and the second memory cell block in the first direction, wherein the pair of second circuit areas comprise row decoder areas, wherein the pair of third circuit areas comprise pass circuit areas including a plurality of pass transistors, wherein the pair of fourth circuit areas comprise page buffer areas as recited in claim 13.
Wherein the first memory cell block and the second memory cell block each comprise: a memory cell area including a plurality of gate lines sequentially stacked along the first direction, and a connection area including a plurality of conductive pad areas integrally connected to the plurality of gate lines, wherein the plurality of conductive pad areas of each of the first and second memory cell blocks decrease in planar area with decreasing distance from the peripheral circuit structure so that a limited cell connection area is formed between the peripheral circuit structure and the plurality of conductive pad areas, wherein, in each of the first memory cell block and the second memory cell block, the memory cell area is spaced apart from the peripheral circuit connection area with the cell connection area therebetween as recited in claim 15.
Further comprising: a first common source line and a second common source line, spaced apart from the peripheral circuit structure in the first direction with a memory cell area of each of the first memory cell block and the second memory cell block therebetween and spaced apart in the second direction with the peripheral circuit connection area therebetween; and a plurality of connection pads between the first common source line and the second common source line in the peripheral circuit connection area and connected to the second end portion of each of the plurality of contact plugs, wherein the plurality of connection pads are arranged at positions spaced apart from the first common source line and the second common source line in the second direction as recited in claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818