DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on June 13, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 27, 2023, March 14, 2024 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device With Reduced Area For Improved Cell Interference and Electronic System Including the Same
Election/Restrictions
Applicant’s election without traverse of Species 1 (Figs. 3-4, Claims 1-20) in the reply filed on September 11, 2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0265384) in view of Chang (US 2002/0142569). Claim 1, Kim discloses (Fig. 1A) a semiconductor device comprising: a conductive pattern (11, conductive layers, Para [0033]) on a substrate (not shown but device including 11 is formed over substrate, Para [0003], hereinafter “sub”), the conductive pattern extending in a lateral direction (11 extends in I direction) parallel to a surface of the substrate (I would be parallel to top surface of sub); an insulating pattern (12/13, insulating layer/insulating pattern, Para [0032] – [0033]) on the substrate (12/13 would be formed on sub), the insulating pattern extending parallel to the conductive pattern in the lateral direction (12/13 extends in I direction parallel to 11); a channel film (17, channel layer, Para [0035]) extending in a vertical direction (17 extends in II direction) to the surface of the substrate (II direction would be vertical to top surface of sub) inside a channel hole (17 is formed inside a hole where CH and M are formed, hereinafter “chole”) passing through the conductive pattern and the insulating pattern (17 is formed inside chole passing through 11 and 12/13); a charge trap pattern (15, data storage layer has charge trapping material, Para [0042]) between the conductive pattern (11) and the channel film inside the channel hole (15 is between 11 and 17 inside chole); a tunneling dielectric film (16,tunnel insulating layer, Para [0042]) between the charge trap pattern and the channel film (16 is between 15 and 17); and a blocking dielectric film (14, blocking layer, Para [0042]) extending in the vertical direction inside the channel hole (14 extends in II direction inside chole) between the conductive pattern and the charge trap pattern (14 is between 11 and 15), and between the insulating pattern and the tunneling dielectric film (14 is between 12/13 and 16), wherein the insulating pattern (12/13) comprises a first insulating pattern (12) overlapping the conductive pattern in the vertical direction (12 overlaps 11 in II direction) and a second insulating pattern (13) protruding in the lateral direction from the first insulating pattern into the channel hole (13 protrudes in I direction from 12 into chole) and toward the channel film (13 protrudes toward 17), the first insulating pattern having a first dielectric constant (12 can be a nitride such as silicon nitride with a dielectric constant, Para [0033]), and the second insulating pattern (13) having a second dielectric constant (13 can be an oxide layer such as silicon oxide with another dielectric constant, Para [0037]). Kim does not explicitly disclose a second dielectric constant that is lower than the first dielectric constant. However, Chang discloses that the dielectric constant of silicon oxide is about 3.9 and the dielectric constant of silicon nitride is about 7.5 (Para [0019]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for 12 to have a lower dielectric constant than 13 as silicon oxide as the materials relatively constant is inherent to the element and can affect coupling ratio and charge gains (Chang, Para [0019]).
Claim 2, Kim in view of Chang discloses the semiconductor device of claim 1. Kim discloses (Fig. 1A) wherein the second insulating pattern (13) narrows toward the channel film (13 vertically narrows as it approaches 17), and a portion of the blocking dielectric film (14) on the second insulating pattern extends in the lateral direction toward the channel film (portion of 14 on 13 extends in I direction towards 17, hereinafter “block”) and beyond a surface of the charge trap pattern (as seen in Fig. 1A, block extends beyond an inner surface of 14). Claim 3, Kim in view of Chang discloses the semiconductor device of claim 1. Kim discloses (Fig. 1A) wherein, in the lateral direction (I direction), a first distance (lateral distance between inner sidewall of 12 and 17, hereinafter “d1”) between a sidewall of the first insulating pattern (12), which is closest to the channel film (17), and the channel film is greater than a second distance (lateral distance between inner sidewall of 11 and 17, hereinafter “d2”) between a sidewall of the conductive pattern (11), which is closest to the channel film, and the channel film (d1 is greater than d2 since 12 is laterally farther than 11). Claim 4, Kim in view of Chang discloses the semiconductor device of claim 1. Kim discloses (Fig. 1A) wherein the second insulating pattern (13) comprises a first portion (flat portion of 13 vertically overlapping 11, hereinafter “1st”) and a second portion (curved portion of 13 vertically overlapping 14, hereinafter “2nd”), the first portion overlapping the conductive pattern in the vertical direction (1st overlaps 11 in II direction), and the second portion overlapping the blocking dielectric film in the vertical direction inside the channel hole (2nd overlaps 14 in II direction inside chole), and a thickness of the second portion is less than a thickness of the first portion in the vertical direction (thickness of 2nd is less than thickness of 1st in II direction since 2nd curves). Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0265384) in view of Han (US 2011/0199825) in view of Chang (US 2002/0142569). Claim 19, Kim discloses (Fig. 1A) a semiconductor device comprises: a conductive pattern (11, conductive layers, Para [0033]) on a substrate (not shown but device including 11 is formed over substrate, Para [0003], hereinafter “sub”), the conductive pattern extending in a lateral direction (11 extends in I direction) parallel to a surface of the substrate (I would be parallel to top surface of sub); an insulating pattern (12/13, insulating layer/insulating pattern, Para [0032] – [0033]) on the substrate (12/13 is on sub), the insulating pattern extending in the lateral direction (12/13 extends in I direction) parallel to the conductive pattern (12/13 is parallel to 11); a channel film (17, channel layer, Para [0035]) extending in a vertical direction (17 extends in II direction) to the surface of the substrate (II direction would be vertical to top surface of sub) inside a channel hole (17 is formed inside a hole where CH and M are formed, hereinafter “chole”) passing through the conductive pattern and the insulating pattern (17 is formed inside chole passing through 11 and 12/13); a charge trap pattern (15, data storage layer has charge trapping material, Para [0042]) between the conductive pattern (11) and the channel film inside the channel hole (15 is between 11 and 17 inside chole); a tunneling dielectric film (16,tunnel insulating layer, Para [0042]) between the charge trap pattern and the channel film (16 is between 15 and 17); and a blocking dielectric film (14, blocking layer, Para [0042]) extending in the vertical direction inside the channel hole (14 extends in II direction inside chole) between the conductive pattern and the charge trap pattern (14 is between 11 and 15), and between the insulating pattern and the tunneling dielectric film (14 is between 12/13 and 16), wherein the insulating pattern (12/13) comprises a first insulating pattern (12) overlapping the conductive pattern in the vertical direction (12 overlaps 11 in II direction) and a second insulating pattern (13) protruding in the lateral direction from the first insulating pattern into the channel hole (13 protrudes in I direction from 12 into chole) and toward the channel film (13 protrudes toward 17), the first insulating pattern having a first dielectric constant (12 can be a nitride such as silicon nitride with a dielectric constant, Para [0033]), and the second insulating pattern (13) having a second dielectric constant (13 can be an oxide layer such as silicon oxide with another dielectric constant, Para [0037]).
Kim does not explicitly disclose an electronic system comprising: a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate.
However, Han discloses (Figs. 1-2 and 4) an electronic system (Fig. 1, 1000, memory system, Para [0123]) comprising: a main substrate (Fig. 4, 111, substrate, Para [0155]); a semiconductor device (100, nonvolatile memory device, Para [0148]) on the main substrate (memory blocks of 100 are formed on 111 as shown in Fig. 4, Para [0154] – [0155]); and a controller (Fig. 2, 150, control logic, Para [0137]) electrically connected to the semiconductor device (150 is connected to memory cell array 110 of 100, Para [0139]) on the main substrate (150 would be formed on 111). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the electronic system of Han to the device of Kim as it allows the memory device to be configured for read, write and erase operations (Han, Para [0125]). Kim in view of Han does not explicitly disclose a second dielectric constant that is lower than the first dielectric constant. However, Chang discloses that the dielectric constant of silicon oxide is about 3.9 and the dielectric constant of silicon nitride is about 7.5 (Para [0019]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for 12 to have a lower dielectric constant than 13 as silicon oxide as the materials relatively constant is inherent to the element and can affect coupling ratio and charge gains (Chang, Para [0019]).
Claim 20, Kim in view of Han and Chang discloses the electronic system of claim 19, wherein the main substrate (111 of Han) further comprises wiring patterns (Fig.2 of Han shows wiring denoted by arrows, hereinafter “wire”) configured to electrically connect the semiconductor device to the controller (wire connects 110 of 100 to 150), and, in the semiconductor device (Kim, Fig. 1A), the second insulating pattern (13) narrows toward the channel film (13 vertically narrows as it approaches 17), and a portion of the blocking dielectric film (14) on the second insulating pattern extends in the lateral direction toward the channel film (portion of 14 on 13 extends in I direction towards 17, hereinafter “block”) and beyond a surface of the charge trap pattern (as seen in Fig. 1A, block extends beyond an inner surface of 14).
Allowable Subject Matter
Claims 5-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Kim (US 2021/0265384), Han (US 2011/0199825), Chang (US 2002/0142569), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 5, and a second portion of the blocking dielectric film is on the second insulating pattern and is in contact with the tunneling dielectric film.
Regarding Claim 6, a protrusion protruding in the lateral direction out of the channel hole and toward the first insulating pattern.
Regarding Claim 7, a protrusion protruding in the lateral direction out of the channel hole and onto a bottom surface or a top surface of the conductive pattern.
Regarding Claim 8, the blocking dielectric film extends in the vertical direction inside the channel hole in a zigzag manner to contact the charge trap pattern at a surface facing the conductive pattern, at a bottom surface facing the substrate, and at a top surface opposite to the bottom surface.
Regarding Claim 9, wherein the tunneling dielectric film comprises a first portion in contact with the charge trap pattern, and a second portion in contact with the blocking dielectric film.
Claims 10-18 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Kim (US 2021/0265384), Han (US 2011/0199825), Chang (US 2002/0142569), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 10 (from which claims 11-18 depend), the plurality of charge trap patterns being spaced apart from each other in the vertical direction… wherein each of the plurality of insulating patterns comprises a first insulating pattern overlapping the plurality of conductive patterns in the vertical direction and a second insulating pattern protruding in the lateral direction from the first insulating pattern into the channel hole and toward the channel film…
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/G.G.R/Examiner, Art Unit 2812