Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments, filed 7/1/26, with respect to the rejection(s) of claim(s) 1-17 under 35 U.S.C 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of HIRATA et al..
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Watanabe et al. (U.S. Patent Publication No. 2009/00298263) in view of HIRATA et al. (U.S. Patent Publication No. 2019/0304769).
Referring to figures 1-13, Watanabe et al. teaches a method comprising: directing a laser beam (32) at a first side surface (21a) of a semiconductor substrate (21) at an entry point along a respective scribe street (22) thereof, wherein the substrate includes a plurality of dies having circuitry (23) at the first side surface and separated from one another by respective scribe streets, the laser beam is focused within the substrate to form a modified region (210) and a crack (211) extending from the modified region (210) towards at least one of the first (21a) and second side surfaces (21b), (see paragraphs# 25, 57, it is noted that the total thickness of the substrate is 600µm);
applying tape (5) on the first side surface (21a) after directing the laser beam (see paragraph# 55, figures 9a-9b); and
backgrinding to reduce a thickness of the substrate from the second side surface to provide a thinned second side surface that intersects an extension of the crack (see paragraphs# 55-56, figures 10a-10b).
However, the reference does not clearly teach the modified region is closer to the first side surface than a second side surface that is opposite the first side surface.
HIRATA et al. teaches forming a wafer having the modified region is closer to the first side surface than a second side surface that is opposite the first side surface.
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form a wafer having the modified region is closer to the first side surface than a second side surface that is opposite the first side surface in Watana et al. as taught by HIRATA et al. because the modification can have greater effect on the active device structures while leaving more of the bulk wafer and backside unaffected.
Regarding to claim 4, directing the laser beam includes a single pass of the laser beam along the respective scribe street to provide a respective single silicon damage layer constituting the modified region within the substrate (see paragraphs# 31-41).
Regarding to claim 6, the circuitry is spaced between the modified region and the first side surface (see figure 5, paragraph# 25).
Regarding to claim 7, the tape is a backgrind tape, the method further comprising: applying a dicing tape to the second side surface of the substrate; and removing the backgrind tape from the first side surface (see figures 11-13, paragraphs# 58-63).
Regarding to claim 8, performing tape expansion to separate the semiconductor dies from one another (see figures 11-13, paragraphs# 58-63).
Regarding to claim 9, a respective semiconductor die produced according to the method of claim 8, wherein: the circuitry (23) in the substrate (21) is at a first location closer to the first side surface (21a) than to the second side surface (21b), the respective semiconductor die includes at least one sidewall surface between the first and second side surfaces thereof, the at least one sidewall surface including a single modified texture region at a second location between a first location and the second side surface, in which the second location is closer to the first side surface than to the second side surface (see paragraphs# 25, 57, see figures 2, 10).
Regarding to claim 10, directing the laser beam includes controlling the laser beam to have a focal point and beam width based on a location of the circuitry relative to the first side surface and a width of the respective scribe street (see figures 11-13, paragraphs# 58-63).
Claim(s) 11-12, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujii et al. (U.S. Patent Publication No. 2005/0272223) in view of HIRATA et al. (U.S. Patent Publication No. 2019/0304769).
Referring to figures 14-35, Fujii et al. teaches a method comprising:
directing a laser beam (L) at a first side surface (3) of a semiconductor substrate (1) at an entry point along a respective scribe street thereof, wherein the substrate (1) includes a plurality of semiconductor die having circuitry (19) at the first side surface and separated from one another by respective scribe streets, the laser beam (L) is focused within the substrate (1) to form a modified region (7/13) and a crack (15) extending from the modified region in a direction orthogonal to the first side surface (see figures 14-20);
applying pressure at the first side surface (3) of the substrate to extend the crack (15) towards the first side surface (see paragraph# 127); and
backgrinding to reduce a thickness of the substrate from the second side surface (21) and provide a thinned second side surface that intersects an extension of the crack (15, see paragraphs# 130-131, figures 17-18).
HIRATA et al. teaches forming a wafer having the modified region is closer to the first side surface than a second side surface that is opposite the first side surface.
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form a wafer having the modified region is closer to the first side surface than a second side surface that is opposite the first side surface in Fujii et al. as taught by HIRATA et al. because the modification can have greater effect on the active device structures while leaving more of the bulk wafer and backside unaffected.
Regarding to claim 12, applying the pressure (force, see paragraph# 127) includes applying tape (20) onto the first side, and backgrinding includes extending a first portion of the crack to intersect with the first side surface and extending a second portion of the crack towards the second side surface (see paragraphs# 130-131, 139-140, figures 17-18, 23)
Regarding to claim 15, directing the laser beam includes a single pass of the laser beam along the respective scribe street to provide a respective single silicon damage layer, constituting the modified region within the substrate, and the method further comprises: applying dicing tape (20) to the second side (21) surface of the substrate (1); and performing tape (20) expansion with the dicing tape to separate the semiconductor dies from one another (see paragraphs# 128-132, 139-140, figures 19-23).
Regarding to claim 16, a respective semiconductor die produced according to the method of claim 15, wherein the respective semiconductor die (19) includes at least one sidewall surface
extending between the first (3) and second side (21) surfaces thereof, the at least one sidewall surface including a single modified texture region at a location between the circuitry (19) and the second side surface that is closer to the first side surface than the second side surface (see figures 17-23, paragraphs# 128-132, 130-140).
Regarding to claim 17, wherein directing the laser beam includes controlling the laser beam to have a focal point and beam width based on a location of the circuitry relative to the first side surface and a width of the respective scribe street (see paragraphs# 121-126).
Claims 2-3, 5, 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al. (U.S. Patent Publication No. 2009/00298263) in view of HIRATA et al. (U.S. Patent Publication No. 2019/0304769) as applied in claim(s) 1, 4, 6-10 or Fujii et al. (U.S. Patent Publication No. 2005/0272223) in view of HIRATA et al. (U.S. Patent Publication No. 2019/0304769) as applied in claims 11-12, 15-17 above, further in view of FURUTA et al. (U.S. Patent Publication No. 2022/0102216).
Referring to figures 1-13, Watanabe et al. teaches a method comprising: directing a laser beam (32) at a first side surface (21a) of a semiconductor substrate (21) at an entry point along a respective scribe street (22) thereof, wherein the substrate includes a plurality of dies having circuitry (23) at the first side surface and separated from one another by respective scribe streets, the laser beam is focused within the substrate to form a modified region (210) and a crack (211) extending from the modified region (210) towards at least one of the first (21a) and second side surfaces (21b), and the modified region is closer to the first side surface than a second side surface that is opposite the first side surface (see paragraphs# 25, 57, it is noted that the total thickness of the substrate is 600µm);
applying tape (5) on the first side surface (21a) after directing the laser beam (see paragraph# 55, figures 9a-9b); and
backgrinding to reduce a thickness of the substrate from the second side surface to provide a thinned second side surface that intersects an extension of the crack (see paragraphs# 55-56, figures 10a-10b).
However, the reference does not clearly teach applying the tape includes sufficient force on the first side surface to extend the crack towards the first side surface, and backgrinding includes extending the crack towards at least one of the first and second side surfaces (in claim 2), applying the tape includes using a roller to press the tape onto the first side surface while supported on the second side surface (in claims 3, 13), the modified region is spaced less than 20 micrometers from the first side surface (in claims 5, 15).
Furuta teaches wafer processing method by applying the tape (20) includes sufficient force on the first side surface to extend the crack towards the first side surface, and backgrinding includes extending the crack towards at least one of the first and second side surfaces (see figure 5, meeting claim 2), applying the tape (20) includes using a roller (25) to press the tape onto the first side surface while supported on the second side surface (see figure 3, meeting claims 3, 13).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to applying the tape includes using a roller to press the tape onto the first side surface while supported on the second side surface in Watanabe et al. or Fujii et al. as taught by Furuta because the process is known in the art to improve adhesion between the wafer and dicing tape.
In re claims 5 and 14, the selection of the spacing is obvious because it is a matter of
determining optimum process condition by routine experimentation with a limited number of
species. ln re Jones, 162 USPQ 224 (CCPA 1955)(the selection of optimum ranges within prior
art general conditions is obvious) and In re Boesch, 205 USPQ 215 (CCPA 1980)(discovery of
optimum value of result effective variable in a known process is obvious). In such a situation, applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to prior art range. See M.P.E.P 2144.05 III.
In particular, Watanabe et al. or Fujii et al. suggest that the spacing can be optimized (see figure 3-5, paragraph# 59 in Watanabe et al.) (see figure 5, paragraph# 59 in Fujii et al.).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to applying the tape includes using a roller to press the tape onto the first side surface while supported on the second side surface in Watanabe et al. or Fujii et al. because the process is known in the art to controlled crack progation and reducued device damage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pairdirect.uspto.gov. Should you have questions on access to thy Private PAIR system, contact the Electronic Business center (EBC) at 866-217-9197 (toll-free).
/THANH T NGUYEN/Primary Examiner, Art Unit 2893
Prosecution Insights