DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance1 or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission (i.e., amended claim set) filed on 06/25/2026 has been entered as of the RCE dated 06/25/2026.
Information Disclosure Statement
The information disclosure statement submitted on 07/02/2026 was filed before first Office action after filing of RCE. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0134806 A1 to Lee et al. (“Lee”) in view of KR 100281272 B1 to Kim.
Regarding claim 1, Lee teaches a semiconductor device, comprising:
a substrate 100 (“substrate (i.e., a semiconductor wafer) 100”; Figs. 1–3; ¶0040);
a chip region I (“the first region I of the substrate 100 may be a chip region”; Fig. 1; ¶0040) in the substrate 100;
a scribe lane region IV (“the fourth region IV of the substrate 100 … may be a scribe lane region”; Fig. 1; ¶0040) in the substrate 100;
first active patterns 105 (“first … active patterns 105 … on the second … region II”; Figs. 3–5; ¶0041) in the chip region I (second region II is the cell region inside first region I; ¶0040);
a first device isolation pattern 110 (“an isolation pattern 110 may be formed on the substrate 100 to cover sidewalls of the first to third active patterns 105, 108 and 109”; Figs. 3–5; ¶0041) on the first active patterns 105 (110 fills the first recess against the sidewalls of 105 and is planarized to the upper surfaces of 105; ¶0041);
second active patterns 109 (“… third active patterns … 109 may be formed on the … fourth region … IV”; Figs. 3–5; ¶0041) in the scribe lane region IV;
and a second device isolation pattern 110 on the second active patterns 109 (the same isolation layer 110 covers sidewalls of 109; ¶0041),
wherein the scribe lane region IV is adjacent to the chip region I (IV is formed between first regions I; Fig. 1; ¶0040),
wherein the first device isolation pattern 110 includes a first device isolation material silicon oxide (“the isolation pattern 110 may include oxide, e.g., silicon oxide”).
Lee teaches that first to third active patterns 105, 108, 109 are defined by removing an upper portion of substrate 100 to form a first recess that isolation pattern 110 fills (¶0041). That first recess between neighboring third active patterns 109 spaces the scribe-lane second active patterns. Lee also teaches second trench 709 between neighboring key structures 309 on fourth region IV, of width W2 greater than cell-side first trench 705 of width W1 (Fig. 12; ¶0058).
Lee uses one isolation pattern 110 of the same silicon oxide in both the chip region I and the scribe lane region IV. Lee therefore does not expressly teach:
second active patterns in the scribe lane region spaced apart from each other by a first trench;
a second device isolation pattern that includes a second device isolation material;
wherein the second device isolation pattern comprises a layer covering a bottom surface of the first trench; and
wherein the second device isolation material is different from the first device isolation material.
Kim teaches a method of forming an element isolation insulating film in which a narrow cell trench and a wide scribe/peripheral trench are filled with physically different oxides (abstract; description of embodiments; Figs. 1A–1E).
Kim teaches:
second active patterns remaining portions of semiconductor substrate 11 in the scribe/peripheral portion in the scribe lane region (“the second trench 21 having a wide width formed on the other side is formed in a scribe region where the device is not formed or a peripheral circuit portion”; Figs. 1A–1E) spaced apart from each other by a first trench 21 (21 is a trench because nitride film 15, first oxide film 13, and substrate 11 are etched using first photoresist pattern 17 as a mask to form an etched groove of large width in the scribe region; Fig. 1A);
a second device isolation pattern 27, 29 (thermal oxide film 27 and second oxide layer 29) on the second active patterns (27 is grown on second trenches 21; 29 is formed to fill first and second trenches 19, 21; Figs. 1C–1D);
wherein the second device isolation pattern 27/29 includes a second device isolation material 27 (thermally grown silicon oxide on the bottom of wide trench 21; Fig. 1C);
wherein the second device isolation pattern 27/29 comprises a layer 27 covering a bottom surface of the first trench 21 (“a thermal oxide film 27 is formed on the second trenches 21”; “the thermal oxide film 27 formed on the second trenches 21 is formed only on the second trenches 21”; Fig. 1C); and
wherein the second device isolation material 27 is different from the first device isolation material 29 in narrow first trench 19.
Kim’s first isolation in the cell portion is the deposited fill in narrow first trench 19: second oxide layer 29 of O3-TEOS, TEOS, HTO, or MTO (description of embodiments). Kim’s second isolation in the scribe portion includes thermal oxide film 27 grown on the bottom of wide second trench 21. Those are physically different materials. Thermal oxide is grown from the silicon substrate and is a dense, stoichiometric SiO2. TEOS/O3-TEOS/HTO/MTO is a deposited film that incorporates residual hydrogen and/or carbon and is less dense. They have different wet-etch rates, different refractive indices, and different resistance to the front-etch / planarization Kim uses. Kim treats them as different films: thermal oxide 27 is formed only in the wide trench by thermal oxidation after implant, and second oxide layer 29 is then deposited over the whole surface to fill both trenches. The cell isolation that remains in narrow trench 19 is the deposited TEOS-type film. The scribe isolation includes the thermally grown film 27 covering the trench bottom. That is a different device isolation material.
Kim’s reason is that deposited oxide in a wide trench is thinner after etch-back than deposited oxide in a narrow cell trench, so the substrate in the wide scribe/periphery is exposed and reliability drops. Kim therefore grows thermal oxide 27 on the bottom of the wide trench and then deposits the TEOS-type fill (description of embodiments).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee so that the isolation spacing the third active patterns 109 in scribe lane region IV (Lee’s first recess between 109, and/or wide second trench 709 of width W2) includes a thermally grown oxide layer covering the trench bottom, while the cell isolation on first active patterns 105 remains a deposited silicon oxide, as taught by Kim. Lee already has a narrow cell spacing (105 / W1) and a wider scribe spacing (109 / W2; Fig. 12; ¶0058). Kim identifies that same narrow-versus-wide problem and supplies a bottom-covering thermal oxide that is a different material from the deposited cell fill, so planarization does not expose the wide-trench substrate. The combination applies Kim’s known isolation materials to Lee’s known wide scribe trench in the same way, with a reasonable expectation of success.
Lee in view of Kim therefore teaches every limitation of claim 1.
Regarding claim 2, Lee in view of Kim teaches the semiconductor device of claim 1.
Lee in view of Kim teaches wherein the first device isolation material 110 / 29 in narrow first trench 19 has a first etching rate,
wherein the second device isolation material 27 has a second etching rate, and
wherein the first etching rate is different from the second etching rate.
Thermal oxide and TEOS-type deposited oxide etch at different rates in the same wet or dry chemistry. That difference is why Kim grows 27 only in the wide trench and then relies on thickness and etch behavior during front etching (description of embodiments). Different materials recited in claim 1 therefore have different etching rates.
Regarding claim 3, Lee in view of Kim teaches the semiconductor device of claim 2.
Kim teaches using the etch difference between the wide-trench thermal oxide and the cell-side deposited oxide so the wide-trench isolation survives front etching that exposes the cell active region (description of embodiments). Setting the second etching rate of thermal oxide film 27 less than or equal to 0.1 times of the first etching rate of the deposited cell oxide is an obvious optimization of that selectivity so the scribe bottom layer is not removed when the cell isolation is recessed. Official notice is taken that thermal oxide versus TEOS, and nitride versus oxide, routinely provide etch-rate ratios of 10:1 or greater in conventional STI chemistries.
Regarding claim 4, Lee in view of Kim teaches the semiconductor device of claim 1.
Lee in view of Kim teaches wherein the first device isolation material includes silicon oxide 110 / 29 in first trench 19, and
wherein the second device isolation material includes silicon nitride 15 (Fig. 1A), silicon carbon nitride, silicon boron nitride, silicon carbon boron nitride, polysilicon, doped polysilicon, and/or a mixture thereof.
Kim forms nitride film 15 on first oxide film 13 as part of forming the isolation. It would have been obvious to leave or use that nitride, or an equivalent nitride liner, as a layer of the scribe isolation because Kim already places nitride in the isolation stack and nitride is etch-selective to the cell oxide. Independently, thermal oxide film 27 itself remains a second isolation material different from the cell silicon oxide, as set forth in claim 1. The Markush is met at least by silicon nitride 15.
Regarding claim 5, Lee in view of Kim teaches the semiconductor device of claim 1, further comprising:
bit line structures 305 (“the bit line structure 305 may extend in the second direction on the second region II of the substrate 100”; Figs. 11–13) in the chip region I; and
key structures 309 (“the key structure 309 may extend in the second direction on the fourth region IV of the substrate 100”; Figs. 11–13) in the scribe lane region IV.
Regarding claim 6, Lee in view of Kim teaches the semiconductor device of claim 5.
Lee teaches wherein the bit line structures 305 include a first conductive structure 269 (third conductive pattern 219 and seventh conductive pattern 259), a first barrier pattern 279 (or first barrier pattern 275), a first metal pattern 289 (or first metal pattern 285), and a first capping pattern 299 (or first capping pattern 295) which are stacked on the substrate 100 (Figs. 11–13).
Regarding claim 7, Lee in view of Kim teaches the semiconductor device of claim 6.
Lee teaches wherein the key structures 309 include an insulation pattern 199 (and/or fourth and fifth insulation patterns 179, 189), a second conductive structure 219, 259, a second barrier pattern 279, a second metal pattern 289, and a second capping pattern 299 which are stacked on the substrate 100 (Figs. 11–13).
Regarding claim 8, Lee in view of Kim teaches the semiconductor device of claim 5.
Lee teaches wherein the bit line structures 305 are spaced apart from each other by a first width W1 of first trench 705 in a first direction parallel to an upper surface of the substrate 100 and extend in a second direction that intersects the first direction (Fig. 12; ¶0058).
Regarding claim 9, Lee in view of Kim teaches the semiconductor device of claim 8.
Lee teaches wherein the key structures 309 are spaced apart from each other by a second width W2 of second trench 709 in the first direction parallel to the upper surface of the substrate 100 and extend in the second direction (Fig. 12; ¶0058).
Regarding claim 10, Lee in view of Kim teaches the semiconductor device of claim 9.
Lee teaches wherein the second width W2 is greater than the first width W1 (“the second trench 709 … may have a second width W2 greater than the first width W1”; Fig. 12; ¶0058).
Regarding claim 11, Lee teaches a semiconductor device, comprising:
a substrate 100 that has a chip region I and a scribe lane region IV that surrounds the chip region I in a plan view (Fig. 1; ¶0040),
wherein the chip region I includes first active patterns 105, a first device isolation pattern 110 on the first active patterns 105, and first gate structures 160 (“the first gate structure 160 may include a first gate insulation layer 130 … a first gate electrode 140 … and a first gate mask 150”; Fig. 4) on respective ones of the first active patterns 105 and on the first device isolation pattern 110 (160 is formed in a second recess etched into 105 and 110; Fig. 4; ¶0042),
wherein the scribe lane region IV includes second active patterns 109 and a second device isolation pattern 110 on the second active patterns 109,
wherein the first device isolation pattern 110 includes a first device isolation material silicon oxide.
Lee does not expressly teach second active patterns spaced apart from each other by a first trench, a second isolation second device isolation material, that second isolation comprises a layer covering a bottom surface of the first trench, and that the second material has an etch selectivity with respect to the first material.
Kim teaches second trench 21 in the scribe region spacing the remaining actives of substrate 11; thermal oxide film 27 covering the bottom surface of 21; deposited second oxide layer 29 of TEOS/HTO/MTO filling narrow first trench 19 in the cell portion; and etch selectivity used in front etching (Figs. 1A–1E; description of embodiments; selectivity of second oxide to substrate of 3:1 to 8:1). Thermal oxide 27 and deposited TEOS-type oxide 29 are physically different materials and therefore have etch selectivity with respect to each other.
The same motivation set forth for claim 1 applies. Lee already has first gate structures 160 on the cell actives and isolation. Substituting Kim’s thermal-oxide bottom layer and deposited cell fill into Lee’s wide scribe isolation versus narrow cell isolation yields the claimed etch selectivity.
Lee in view of Kim therefore teaches every limitation of claim 11.
Regarding claim 12, Lee in view of Kim teaches the semiconductor device of claim 11.
Lee teaches wherein the first gate structures 160 each includes a first gate insulation layer 130 on the first active patterns 105 and the substrate 100 (130 is thermal oxide on the surface of 105 exposed by the second recess; Fig. 4), a first gate electrode 140 on the first gate insulation layer 130, and a first gate mask 150 on the first gate electrode 140 (Fig. 4).
Regarding claim 13, Lee in view of Kim teaches the semiconductor device of claim 11.
Lee teaches wherein the first gate structures 160 extend in a first direction parallel to an upper surface of the substrate 100 and are spaced apart from each other in a second direction that intersects the first direction (the second recess receiving 160 extends in the first direction; gates on neighboring first active patterns 105 are spaced in the crossing direction; Figs. 3–5; ¶0041–0042).
Regarding claim 14, Lee teaches a semiconductor device, comprising:
a substrate 100 that has a chip region I, and a scribe lane region IV that surrounds the chip region I in a plan view (Fig. 1; ¶0040);
bit line structures 305 on the chip region I; and
key structures 309 on the scribe lane region IV,
wherein the chip region I includes first active patterns 105, a first device isolation pattern 110 between the first active patterns 105 (110 fills the first recess between neighboring 105; ¶0041), and first gate structures 160 on respective ones of the first active patterns 105 and on the first device isolation pattern 110 (Fig. 4),
wherein the scribe lane region IV includes second active patterns 109 and a second device isolation pattern 110 between the second active patterns 109,
wherein the first device isolation pattern 110 includes a first device isolation material silicon oxide.
Lee does not expressly teach second active patterns spaced apart from each other by a first trench, a second isolation second device isolation material, a layer covering a bottom surface of the first trench, and etch selectivity of the second material with respect to the first material.
Kim teaches those limitations as in claims 1 and 11: wide second trench 21 in the scribe region; thermal oxide film 27 covering the bottom of 21; deposited TEOS-type second oxide layer 29 in narrow cell first trench 19; physically different materials with etch selectivity.
The same motivation set forth for claim 1 applies. Lee already supplies bit lines 305, keys 309, gates 160, and isolation between actives.
Lee in view of Kim therefore teaches every limitation of claim 14.
Regarding claim 15, Lee in view of Kim teaches the semiconductor device of claim 14.
Lee teaches wherein the bit line structures 305 are spaced apart from each other by a first width W1 in a first direction parallel to an upper surface of the substrate 100 and extend in a second direction that intersects the first direction (Fig. 12; ¶0058).
Regarding claim 16, Lee in view of Kim teaches the semiconductor device of claim 14.
Lee teaches wherein the key structures 309 are spaced apart from each other by a second width W2 in a first direction parallel to an upper surface of the substrate 100 and extend in a second direction that intersects the first direction (Fig. 12; ¶0058).
Regarding claim 17, Lee in view of Kim teaches the semiconductor device of claim 14.
Lee teaches wherein the first gate structures 160 extend in a first direction parallel to an upper surface of the substrate 100 and are spaced apart from each other in a second direction that intersects the first direction (Figs. 3–5; ¶0041–0042).
Regarding claim 18, Lee in view of Kim teaches the semiconductor device of claim 14, further comprising:
a lower contact plug 405 (“the lower contact plug 405 extending … between the bit line structures 305”; Figs. 20–22) on a respective one of the first active patterns 105 and the first device isolation pattern 110 between the bit line structures 305; and
an upper contact plug 455 on the lower contact plug 405 (“the lower contact plug 405 … and the upper contact plug 455 sequentially stacked … may form a first contact plug structure”; Fig. 31).
Regarding claim 19, Lee in view of Kim teaches the semiconductor device of claim 18, further comprising:
a fill pattern 409 (“a filling pattern 409 may be formed between the key structures 309”; “the filling pattern 409 may be formed on the isolation pattern 110”; Figs. 13, 20) on the second device isolation pattern 110 as modified by Kim’s 27/29 between the key structures 309; and
an upper contact layer 450 / 459 on the second active patterns 109 and the key structures 309 (Figs. 25–31).
Regarding claim 20, Lee in view of Kim teaches the semiconductor device of claim 19, further comprising:
a capacitor 540 on the upper contact plug 455, wherein the capacitor 540 includes a lower electrode 510 on the upper contact plug 455, a dielectric layer 520 on the lower electrode 510, and an upper electrode 530 on the dielectric layer 520 (Figs. 35–37).
Lee teaches the DRAM chip/scribe layout. Kim teaches that the wide scribe trench gets a thermally grown bottom oxide and the narrow cell trench gets a deposited TEOS-type fill—physically different isolation materials—so the wide trench does not punch through during planarization. That combination meets claims 1–20.
Conclusion
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10 September 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
1 Notice of Allowance dated 02 April 2026
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