Detailed Action
This office action is in response to the amendment filed on February 12th, 2026. Claims 1-30 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed February 12th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 7-9, “Remarks”) that Chang and the other cited references fail to teach the limitations presented in amended Claim 1.
However, as seen below, Claim 1 is now rejected by the combination of Chang, Bisi, Suh, and Xia.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Applicant argues (pgs. 9-11, “Remarks”) that, in the transistors of Xia, a 2DEG forms at the “band offset layer”/channel interface. (Xia, paras, [0060] and [0075] and FIGS. 3A-3D, FIG. 4, and FIG. 5) Therefore, although Xia refers to the layer forming an interface with the channel layer as a "band offset layer," that layer is akin to a "barrier layer" as such layers are understood in the context of the present invention. Xia does not teach that the band offset layer in the transistors disclosed therein comprises AlxGa1-xN where 0.3 ≤ x, as recited in independent claims 10 and 19. The only AlGaN band offset layer composition taught in Xia is the Al0.15Ga0.85N band offset layer shown in FIG. 5, and Xia provides no reason to double the Al fraction in the AlGaN of the band offset layer to 0.3. Xia also fails to disclose a trench layer on the band offset layer comprising an (Al,Ga)N alloy having an aluminum content that is 15 mol.0% lower than that of the AlxGa1-xN of the band offset layer. In Xia's transistors the layer on the band offset layer is a "lower barrier layer" (12), which is composed of AlN or a wet-etchable BwAlxInyGazN (where x > 0.5) and is used as an etch stop for the dry etching of the overlying "upper barrier layer" (10). (Xia, paras. [0042] and [0050].) Therefore, Xia teaches that the layer on the band offset layer has a higher Al fraction than the underlying AlGaN band offset layer. This is the opposite of the requirement in independent claim 10.
However, the examiner notes that the embodiment of Xia used for the rejection of Claims 10 and 19 is shown in Figs. 1A-D. Applicant incorrectly refers to Figs 3-5 when defining the barrier layer and when comparing Al concentrations and incorrectly defines feature 32 as the barrier layer. As seen in more detail below, the trench layer (10) has an aluminum content at least 15 mol.% lower (10 is up to 25% Al while 12 is greater than 50% Al) than the barrier layer (12). In this embodiment, the feature 32 is not formed and is therefore irrelevant to the comparison of Al concentrations.
Therefore, applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1-3, 5-6, 21, 27, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (2021/0036138 A1; hereinafter Chang) in view of Bisi et al. (2025/0185274 A1; hereinafter Bisi), Suh et al (2009/0072240 A1; hereinafter Suh), and Xia et al. (2016/0300835 A1; hereinafter Xia).
Regarding Claim 1, Chang (fig. 3) teaches a high electron mobility transistor ([0036], 2) comprising:
a channel layer ([0036], 104) comprising Ga-polar unintentionally-doped GaN ([0036]);
a barrier layer ([0036], 106) comprising AlxGa1-xN where 0.3 ≤ x ([0038], 106 may be x = .3), InxAl1-xN, where x < 0.25, or InxGayAl1-(x+y)N, where (x+y) < 0.8;
an AlN intervening layer disposed between the channel layer and the barrier layer;
a two-dimensional electron gas ([0042], 2DEG) confined in the channel layer (104);
an etch stop layer ([0036], 108) on the barrier layer, the etch stop layer comprising AlN ([0036]) or an AlGaN alloy having an aluminum content at least 15 mol.% greater ([0038], 108 is 100% Al while 106 is 30% Al) than the aluminum content of the barrier layer (106);
a trench layer ([0036], 116) on the etch stop layer (108), the trench layer (116) comprising an (Al,Ga)N alloy ([0036]) having an aluminum content at least 15 mol.% lower ([0038], 116 is up to 50% Al while 108 is 100% Al) than the aluminum content of the etch stop layer (108);
a source ([0044], 212) in electrical communication with the two-dimensional electron gas (212 extends into 2DEG);
a drain (213) in electrical communication with the two-dimensional electron gas (213 extends into 2DEG); and
a gate ([0040], [0044], 110, 112, 211) between the source (212) and the drain (213), wherein a portion of the gate (110, 112, 211) is recessed ([0040], 110 contacts 108) through the trench layer (116) down to the etch stop layer (108), wherein
the high electron mobility transistor is a depletion mode high electron mobility transistor in which the two-dimensional electron gas is present under the gate at a zero gate voltage.
Chang doesn’t explicitly teach that the channel layer comprising Ga-polar unintentionally-doped GaN.
However, Bisi (fig. 3A) teaches the channel layer ([0077], 12) comprising Ga-polar ([0043]-[0044]) unintentionally-doped GaN ([0077]). One of ordinary skill in the art would have found it obvious to try Ga-polar unintentionally-doped GaN for a channel layer and yielded the predictable results of a functional HEMT.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to try Ga-polar unintentionally-doped GaN for a channel layer since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Chang doesn’t teach an AlN intervening layer disposed between the channel layer and the barrier layer.
However, Suh (fig. 9A) teaches an AlN intervening layer ([0047], 62) disposed between the channel layer ([0047], 61) and the barrier layer ([0047], 63). Suh also teaches that including an AlN interlayer can reduce the required thickness of an AlGaN barrier layer ([0005], [0037], see fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Chang to include the AlN intervening layer of Suh to reduce the required thickness of the AlGaN barrier layer.
Chang doesn’t teach the high electron mobility transistor is a depletion mode high electron mobility transistor in which the two-dimensional electron gas is present under the gate at a zero gate voltage.
However, Xia (fig. 10) teaches the high electron mobility transistor ([0037]) is a depletion mode high electron mobility transistor ([0093], 1010/1020 may be a depletion mode transistor) in which the two-dimensional electron gas ([0060], 2DEG) is present under the gate ([0093], 1012/1022) at a zero gate voltage ([0062]). One of ordinary skill in the art would have found it obvious to try forming a depletion mode transistor and yielded the predictable results of forming a HEMT.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to form a depletion mode transistor since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 2, Chang (fig. 3) teaches the high electron mobility transistor of claim 1, wherein the barrier layer (106), etch stop layer (108), and trench layer (116) have combined thickness of at least 10 nm ([0043], 116 alone may be larger than 10 nm).
Regarding Claim 3, Chang (fig. 3) teaches the high electron mobility transistor of claim 1, wherein the barrier layer comprises the AlxGa1-xN where 0.3 ≤ x < 0.5 ([0038], 106 may be x = .3).
Regarding Claim 5, Chang doesn’t teach the high electron mobility transistor of claim 1, wherein the (Al,Ga)N alloy of the trench layer has an AlN/GaN superlattice structure or an AlGaN/GaN superlattice structure.
However, Xia (fig. 10) teaches the (Al,Ga)N alloy of the trench layer ([0080], 608) has an AlN/GaN ([0080], odd layers may be GaN, even layers may be AlN) superlattice structure or an AlGaN/GaN superlattice structure. Xia also teaches that the superlattice structure allows for further control of gate trench depth by only selectively etching subsets of the structure ([0082]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Chang to include the superlattice trench layer of Xia to control gate trench depth.
Regarding Claim 6, Chang doesn’t teach the high electron mobility transistor of claim 1, wherein the trench layer comprises a first sublayer comprising either GaN or an AlGaN alloy having an Al content of less than 10 mol.% on the etch stop layer and a second sublayer comprising the (Al,Ga)N alloy having an aluminum content at least 15 mol.% lower than the aluminum content of the etch stop layer.
However, Suh (fig. 9A) teaches the trench layer ([0047], 64, 65) comprises a first sublayer comprising either GaN ([0047], 64) or an AlGaN alloy having an Al content of less than 10 mol.% on the etch stop layer ([0047], 63) and a second sublayer comprising the (Al,Ga)N alloy ([0047], 65). Suh teaches this maintains etch selectivity between the trench layer and the etch stop layer ([0044]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Chang to include the trench layer of Suh to maintain etch selectivity between the trench layer and the barrier layer. The combination of Chang and Suh teaches having a second sublayer comprising the (Al,Ga)N alloy (Suh, [0047], for example, 65 may be 20% aluminum) an aluminum content at least 15 mol.% lower than the aluminum content of the etch stop layer (Chang, 108 is 100% aluminum).
Regarding Claim 21, Chang (fig. 3) teaches the high electron mobility transistor of claim 1, wherein the barrier layer (106) has a thickness of at least 10 nm ([0048], 106 may be 10 nm).
Regarding Claim 27, Chang doesn’t teach the high electron mobility transistor of claim 1, wherein the gate is a T- shaped gate.
However, Xia (figs. 1A-D) teaches the gate ([0058], 20) is a T-shaped gate (see fig. 1D). Xia teaches the shape of the gate may be modified while still yielding the predictable results of forming a functional gate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the gate of Xia for the gate of Chang, since simple substitution of gates for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 30, Chang (fig. 1) teaches the high electron mobility transistor of claim 1, wherein the channel layer (104) is on a semi-insulating substrate ([0034], buffer layer 102 may be AlN which is insulating).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, Bisi, Suh, and Xia as applied to Claim 1 above, and further in view of Zhang (2011/0089468 A1; hereinafter Zhang).
Regarding Claim 4, Chang doesn’t teach the high electron mobility transistor of claim 1, wherein the aluminum content of the (Al,Ga)N alloy of the trench layer is graded through the thickness of the trench layer.
However, Zhang (fig. 10) teaches the aluminum content of the (Al,Ga)N alloy of the trench layer ([0066], 17 may have Al composition that gradually increases) is graded through the thickness of the trench layer (17). Zhang also teaches that this allows the trench layer to be made thicker, which is suitable for the gate ([0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Chang to include the graded trench layer of Zhang to form a thicker trench layer for the gate.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, Bisi, Suh, and Xia as applied to Claim 1 above, and further in view of Hwang et al. (2012/0086049 A1; hereinafter Hwang).
Regarding Claim 7, Chang doesn’t teach the high electron mobility transistor of claim 1, wherein the AlxGa1-xN, InxAl1-xN, or InxGayAl1-(x+y)N of the barrier layer has a graded composition.
However, Hwang (fig. 1) teaches the AlxGa1-xN, InxAl1-xN, or InxGayAl1-(x+y)N of the barrier layer ([0064], 40) has a graded composition ([0064]). Hwang also teaches this forms a polarization density gradient in the barrier layer ([0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Chang to include the graded barrier layer of Hwang to provide a polarization density gradient in the barrier layer.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, Bisi, Suh, and Xia as applied to Claim 1 above, and further in view of Hirler et al. (2015/0129929 A1; hereinafter Hirler).
Regarding Claim 8, Chang doesn’t teach the high electron mobility transistor of claim 1, wherein the AlxGa1-xN, InxAl1-xN, or InxGayAl1-(x+y)N of the barrier layer has a superlattice structure.
However, Hirler (fig. 4) teaches the AlxGa1-xN, InxAl1-xN, or InxGayAl1-(x+y)N of the barrier layer ([0056], 63) has a superlattice structure. One of ordinary skill in the art could have substituted the barrier layer of Hirler for the barrier layer of Xia and yielded the predictable results of a functional high electron mobility transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the barrier layer of Hirler for the barrier layer of Xia, since simple substitution of barrier layers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, Bisi, Suh, and Xia as applied to Claim 1 above, and further in view of Moon et al. (2021/0013307 A1; hereinafter Moon).
Regarding Claim 9, Chang doesn’t teach the high electron mobility transistor of claim 1, further comprising a layer comprising graded AlxGa1-xN, where x ranges from 0 to 0.1 disposed between the AlN interlayer and the channel layer.
However, Moon (fig. 8) teaches a layer comprising graded AlxGa1-xN ([0057], 18), where x ranges from 0 to 0.1 ([0058], x ranges from 0 to 0.2) disposed between the AlN interlayer ([0060], 22) and the channel layer ([0057], 14). Moon also teaches the layer may be graded to form a desirable high breakdown voltage device ([0010]-[0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Chang to include the graded layer of Moon to form a desirable high breakdown voltage device.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, Bisi, Suh, and Xia as applied to Claim 1 above, and further in view of Makabe (2019/0043978 A1; hereinafter Makabe).
Regarding Claim 24, Chang doesn’t teach the high electron mobility transistor of claim 1, wherein the source and the drain comprises regrown highly n-type (n++) GaN having an n-type dopant concentration of at least 1020/cm3.
However, Makabe (fig. 1) teaches the source ([0018], 7, 9) and the drain ([0018], 8, 10) comprises regrown highly n-type (n++) GaN having an n-type dopant concentration of at least 1020/cm3 ([0023], 7 and 8 are made of GaN doped up to 1021/cm3). Makabe also teaches that regrowth of GaN layers for the source and drain electrode helps reduce the contact resistance and the access resistance ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Chang to include the regrown GaN source and drain of Makabe to form reduce contact and access resistance.
Claims 10-11, 15, 19-20, 22-23, 28-29, and 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over Xia in view of Bisi and Suh.
Regarding Claim 10, Xia (figs. 1A-D) teaches a high electron mobility transistor ([0042], 1) comprising:
a channel layer ([0042], 6) comprising Ga-polar unintentionally-doped GaN ([0045]);
a barrier layer ([0042], 12) comprising AlxGa1-xN where 0.3 ≤ x ([0050], 12 may have more than 50% Al), InxAl1-xN, where x < 0.25, or InxGayAl1-(x+y)N, where (x+y) < 0.8;
an AlN intervening layer disposed between and adjacent to the channel layer and the barrier layer;
a two-dimensional electron gas ([0060], 2DEG, see fig. 5) confined in the channel layer (6);
a trench layer ([0042], 10) on the barrier layer (12), the trench layer (10) comprising an (Al,Ga)N alloy ([0048], 10 may have up to 25% Al) having an aluminum content at least 15 mol.% lower (10 is up to 25% Al while 12 is greater than 50% Al) than the aluminum content of the AlxGa1-xN, InxAl1-xN, or InxGayAl1-(x+y)N in the barrier layer (12);
a source ([0058], S) in electrical communication (S extends through to 6, see fig. 1D) with the two-dimensional electron gas (2DEG);
a drain ([0058], D) in electrical communication (D extends through to 6, see fig. 1D) with the two-dimensional electron gas (2DEG); and
a gate ([0058], 18, 20) between the source (S) and the drain (D), wherein a portion of the gate (18, 20) is recessed through the trench layer (10, see fig. 1D) down to the barrier layer (12).
Xia doesn’t explicitly teach that the channel layer comprising Ga-polar unintentionally-doped GaN.
However, Bisi (fig. 3A) teaches the channel layer ([0077], 12) comprising Ga-polar ([0043]-[0044]) unintentionally-doped GaN ([0077]). One of ordinary skill in the art would have found it obvious to try Ga-polar unintentionally-doped GaN for a channel layer and yielded the predictable results of a functional HEMT.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to try Ga-polar unintentionally-doped GaN for a channel layer since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Xia doesn’t teach an AlN intervening layer disposed between and adjacent to the channel layer and the barrier layer.
However, Suh (fig. 9A) teaches an AlN intervening layer ([0047], 62) disposed between and adjacent to (62 is directly adjacent to both 61 and 63, see fig. 9A) the channel layer ([0047], 61) and the barrier layer ([0047], 63). Suh also teaches that including an AlN interlayer can reduce the required thickness of an AlGaN barrier layer ([0005], [0037], see fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Xia to include the AlN intervening layer of Suh to reduce the required thickness of the AlGaN barrier layer.
Regarding Claim 11, Xia (figs. 1A-D) teaches the high electron mobility transistor of claim 10, wherein the barrier layer (12) and trench layer (10) have combined thickness of at least 10 nm ([0097], gate recesses are 30 nm, so 12 and 10 also combine to a thickness of at least 30 nm).
Regarding Claim 15, Xia doesn’t teach the high electron mobility transistor of claim 10, wherein the trench layer comprises a first sublayer either GaN or an AlGaN alloy having an Al content of less than 10 mol.% on the barrier layer and a second sublayer comprising the (Al,Ga)N alloy having an aluminum content at least 10 mol.% lower than the aluminum content of the barrier layer.
However, Suh (fig. 9A) teaches the trench layer ([0047], 64, 65) comprises a first sublayer either GaN ([0047], 64) or an AlGaN alloy having an Al content of less than 10 mol.% on the barrier layer ([0047], 63) and a second sublayer comprising the (Al,Ga)N alloy ([0047], 65). Suh teaches this maintains etch selectivity between the trench layer and the barrier layer ([0044]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Xia to include the trench layer of Suh to maintain etch selectivity between the trench layer and the barrier layer.
Additionally, Suh doesn’t explicitly teach a second sublayer comprising the (Al,Ga)N alloy having an aluminum content at least 10 mol.% lower than the aluminum content of the barrier layer. However, Suh does teach that the aluminum content of the second sublayer (65) may be less than ([0047], aluminum content y of 65 may be less than the aluminum content x of 63) the aluminum content of the barrier layer (63). Suh also showcases an example wherein the aluminum content difference is 10 mol.% ([0049], y = .3, x = .2) and that the thicknesses may be modified to accommodate various aluminum contents ([0049]). The aluminum contents of the second sublayer would have been obvious to one of ordinary skill in the art to be a condition to optimize and control through routine experimentation, since the aluminum content is a result-effective variable, that is, a variable which achieves a recognized result, as stated in MPEP § 2144.05. In this case, the aluminum content will determine the required thickness of the second sublayer. It has been well established that the optimum or workable ranges of a result-effective variable can be characterized as routine experimentation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a second sublayer comprising the (Al,Ga)N alloy having an aluminum content at least 10 mol.% lower than the aluminum content of the barrier layer because it controls the thicknesses of the layers and because generally, differences in aluminum content will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such aluminum content is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding Claim 19, Xia (figs. 1A-D) teaches a high electron mobility transistor ([0042], 1) comprising:
a channel layer ([0042], 6) comprising Ga-polar unintentionally-doped GaN ([0045]);
a barrier layer ([0042], 10, 12) having a thickness, t2, of at least 10 nm ([0097], gate recesses are 30 nm, so 12 and 10 also combine to a thickness of at least 30 nm) and comprising AlxGa1-xN where 0.3 ≤ x ([0050], 12 may have more than 50% Al), InxAl1-xN, where x < 0.25, or InxGayAl1-(x+y)N, where (x+y) < 0.8;
an AlN interlayer disposed between and adjacent to the channel layer and the barrier layer;
a two-dimensional electron gas ([0060], 2DEG, see fig. 5) confined in the channel layer (6);
a source ([0058], S) in electrical communication (S extends through to 6, see fig. 1D) with the two-dimensional electron gas (2DEG);
a drain ([0058], D) in electrical communication (D extends through to 6, see fig. 1D) with the two-dimensional electron gas (2DEG); and
a gate ([0058], 18, 20) between the source (S) and the drain (D), wherein a portion of the gate (18, 20) is recessed through the trench layer (10, see fig. 1D) into the barrier layer (12).
Xia doesn’t explicitly teach that the channel layer comprising Ga-polar unintentionally-doped GaN.
However, Bisi (fig. 3A) teaches the channel layer ([0077], 12) comprising Ga-polar ([0043]-[0044]) unintentionally-doped GaN ([0077]). One of ordinary skill in the art would have found it obvious to try Ga-polar unintentionally-doped GaN for a channel layer and yielded the predictable results of a functional HEMT.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to try Ga-polar unintentionally-doped GaN for a channel layer since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Xia doesn’t teach an AlN interlayer disposed between and adjacent to the channel layer and the barrier layer.
However, Suh (fig. 9A) teaches an AlN intervening layer ([0047], 62) disposed between and adjacent to (62 is directly adjacent to both 61 and 63, see fig. 9A) the channel layer ([0047], 61) and the barrier layer ([0047], 63). Suh also teaches that including an AlN interlayer can reduce the required thickness of an AlGaN barrier layer ([0005], [0037], see fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Xia to include the AlN intervening layer of Suh to reduce the required thickness of the AlGaN barrier layer.
Regarding Claim 20, Xia (figs. 1A-D) teaches the high electron mobility transistor of claim 19, wherein the barrier layer (10, 12) comprises the AlxGa1-xN ([0048], [0050]).
Regarding Claim 22, Xia (figs. 1A-D) teaches high electron mobility transistor of claim 10, wherein the high electron mobility transistor ([0037]) is a depletion mode high electron mobility transistor ([0093], transistors may be depletion mode) in which the two-dimensional electron gas ([0060], 2DEG) is present under the gate (18/20) at a zero gate voltage ([0062]).
Regarding Claim 23, Xia (figs. 1A-D) teaches high electron mobility transistor of claim 19, wherein the high electron mobility transistor ([0037]) is a depletion mode high electron mobility transistor ([0093], transistors may be depletion mode) in which the two-dimensional electron gas ([0060], 2DEG) is present under the gate (18/20) at a zero gate voltage ([0062]).
Regarding Claim 28, Xia (figs. 1A-D) teaches the high electron mobility transistor of claim 10, wherein the gate (20) is a T- shaped gate (see fig. 1D).
Regarding Claim 29, Xia (figs. 1A-D) teaches the high electron mobility transistor of claim 19, wherein the gate (20) is a T- shaped gate (see fig. 1D).
Regarding Claim 31, Xia (figs. 1A-D) teaches the high electron mobility transistor of claim 10, wherein the channel layer (6) is on a semi-insulating substrate ([0047], buffer layer 4 may be AlN/GaN).
Regarding Claim 32, Xia (figs. 1A-D) teaches the high electron mobility transistor of claim 19, wherein the channel layer (6) is on a semi-insulating substrate ([0047], buffer layer 4 may be AlN/GaN).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Xia, Bisi, and Suh as applied to Claim 10 above, and further in view of Zhang.
Regarding Claim 13, Xia doesn’t teach the high electron mobility transistor of claim 1, wherein the aluminum content of the (Al,Ga)N alloy of the trench layer is graded through the thickness of the trench layer.
However, Zhang (fig. 10) teaches the aluminum content of the (Al,Ga)N alloy of the trench layer ([0066], 17 may have Al composition that gradually increases) is graded through the thickness of the trench layer (17). Zhang also teaches that this allows the trench layer to be made thicker, which is suitable for the gate ([0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Xia to include the graded trench layer of Zhang to form a thicker trench layer for the gate.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Xia, Bisi, and Suh as applied to Claim 1 above, and further in view of another embodiment of Xia.
Regarding Claim 14, Xia doesn’t teach the high electron mobility transistor of claim 10, wherein the (Al,Ga)N alloy of the trench layer has an AlN/GaN superlattice structure.
However, another embodiment of Xia (fig. 10) teaches the (Al,Ga)N alloy of the trench layer ([0080], 608) has an AlN/GaN ([0080], odd layers may be GaN, even layers may be AlN) superlattice structure or an AlGaN/GaN superlattice structure. Xia also teaches that the superlattice structure allows for further control of gate trench depth by only selectively etching subsets of the structure ([0082]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Xia to include the superlattice trench layer of another embodiment of Xia to control gate trench depth.
Claims 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Xia, Bisi, and Suh as applied to Claim 10 above, and further in view of Hwang.
Regarding Claim 12, Xia doesn’t explicitly teach the high electron mobility transistor of claim 10, wherein the barrier layer comprises the AlxGa1-xN, where 0.30 ≤ x < 0.5.
However, Hwang (fig. 1) teaches the barrier layer ([0064], 40) comprises the AlxGa1-xN, where 0.30 ≤ x < 0.5 ([0064], 40 ranges from 10 to 50% Al). One of ordinary skill in the art could have substituted the barrier layer of Hwang for the barrier layer of Xia and yielded the predictable results of a functional high electron mobility transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the barrier layer of Hwang for the barrier layer of Xia, since simple substitution of barrier layers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 16, Xia doesn’t teach the high electron mobility transistor of claim 10, wherein the AlxGa1-xN, InxAl1-xN, or InxGayAl1-(x+y)N of the barrier layer has a graded composition.
However, Hwang (fig. 1) teaches the AlxGa1-xN, InxAl1-xN, or InxGayAl1-(x+y)N of the barrier layer ([0064], 40) has a graded composition ([0064]). Hwang also teaches this forms a polarization density gradient in the barrier layer ([0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Xia to include the graded barrier layer of Hwang to provide a polarization density gradient in the barrier layer.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Xia, Bisi, and Suh as applied to Claim 10 above, and further in view of Hirler.
Regarding Claim 17, Xia doesn’t teach the high electron mobility transistor of claim 10, wherein the AlxGa1-xN, InxAl1-xN, or InxGayAl1-(x+y)N of the barrier layer has a superlattice structure.
However, Hirler (fig. 4) teaches the AlxGa1-xN, InxAl1-xN, or InxGayAl1-(x+y)N of the barrier layer ([0056], 63) has a superlattice structure. One of ordinary skill in the art could have substituted the barrier layer of Hirler for the barrier layer of Xia and yielded the predictable results of a functional high electron mobility transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the barrier layer of Hirler for the barrier layer of Xia, since simple substitution of barrier layers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Xia, Bisi, and Suh as applied to Claim 10 above, and further in view of Moon.
Regarding Claim 18, Xia doesn’t teach the high electron mobility transistor of claim 1, further comprising a layer comprising graded AlxGa1-xN, where x ranges from 0 to 0.1 disposed between the AlN interlayer and the channel layer.
However, Moon (fig. 8) teaches a layer comprising graded AlxGa1-xN ([0057], 18), where x ranges from 0 to 0.1 ([0058], x ranges from 0 to 0.2) disposed between the AlN interlayer ([0060], 22) and the channel layer ([0057], 14). Moon also teaches the layer may be graded to form a desirable high breakdown voltage device ([0010]-[0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Xia to include the graded layer of Moon to form a desirable high breakdown voltage device.
Claims 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Xia, Bisi, and Suh as applied to Claims 10 and 19 above, and further in view of Makabe.
Regarding Claim 25, Xia doesn’t teach the high electron mobility transistor of claim 10, wherein the source and the drain comprises regrown highly n-type (n++) GaN having an n-type dopant concentration of at least 1020/cm3.
However, Makabe (fig. 1) teaches the source ([0018], 7, 9) and the drain ([0018], 8, 10) comprises regrown highly n-type (n++) GaN having an n-type dopant concentration of at least 1020/cm3 ([0023], 7 and 8 are made of GaN doped up to 1021/cm3). Makabe also teaches that regrowth of GaN layers for the source and drain electrode helps reduce the contact resistance and the access resistance ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Xia to include the regrown GaN source and drain of Makabe to form reduce contact and access resistance.
Regarding Claim 26, Xia doesn’t teach the high electron mobility transistor of claim 19, wherein the source and the drain comprises regrown highly n-type (n++) GaN having an n-type dopant concentration of at least 1020/cm3.
However, Makabe (fig. 1) teaches the source ([0018], 7, 9) and the drain ([0018], 8, 10) comprises regrown highly n-type (n++) GaN having an n-type dopant concentration of at least 1020/cm3 ([0023], 7 and 8 are made of GaN doped up to 1021/cm3). Makabe also teaches that regrowth of GaN layers for the source and drain electrode helps reduce the contact resistance and the access resistance ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the high electron mobility transistor of Xia to include the regrown GaN source and drain of Makabe to form reduce contact and access resistance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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