DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Specie A (Claims 1-11) in the reply filed on 8/29/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2017/0110650) in view of Cheng et al (US 2019/0259855).
With respect to Claim 1, Park et al discloses a magnetic memory device (Figure 4) comprising:
a substrate (Figure 4, 100); a data storage pattern (Figure 4, 150) on the substrate (Figure 4, 100); and a lower contact plug (Figure 4, 140) between the substrate and the data storage pattern (Figure 4, 150); wherein the lower contact plug (Figure 4, 140) includes; a lower contact pattern (Figure 4, 143) and a lower barrier (Figure 4, 141) extending on a side surface of the lower contact pattern. See Figure 4 and corresponding text, 67-78.
However, Park et al does not disclose the presence of “a lower insulating pattern on the substrate”, and its position, wherein the lower contact pattern is on the lower insulating pattern and the lower barrier extending on a lower surface and a side surface of the lower insulating pattern and a side surface of the lower contact pattern.
Cheng et al pertains to contact plugs comprising barrier layers, and discloses a lower insulating pattern (Figure 9, 132) on the substrate (Figure 9, 102) , wherein the lower contact pattern (Figure 9, 138a) is on the lower insulating pattern (Figure 9, 132) and the lower barrier (Figure 9, 134) extending on a lower surface and a side surface of the lower insulating pattern (Figure 9, 132) and a side surface of the lower contact pattern (Figure 9, 138a), and its benefit of contact resistance reduction. See Figure 9, and corresponding text, especially paragraphs 19-35.
It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to modify the device of Park et al to include a lower insulating pattern as disclosed by Cheng et al, for its known benefit in the art of reducing contact resistance. The use of a known element, lower insulating pattern, for its known benefit, reducing contact resistance, would have been prima facie obvious to one of ordinary skill in the art.
With respect to Claim 2, Park et al discloses wherein the data storage pattern (Figure 4, 150) includes a lower electrode (Figure 4, BE) , a magnetic tunnel junction pattern (Figure 4, FL, TBL and RL) , and an upper electrode stacked (Figure 4, TE) on the lower contact plug (Figure 4, 140). See Figure 4 and corresponding text, especially paragraphs 78-83.
With respect to Claim 3, Park et al discloses wherein the lower contact pattern and the lower barrier pattern includes TaN and/or Tin (paragraph 67 and 72) . With respect to the limitation “wherein the lower insulating pattern includes oxide”, the Examiner takes Official Notice that silicon nitride, silicon oxynitride and silicon oxide are notoriously well known dielectrics used in barrier layers and spacers in the semiconductor art. See for example paragraph 60 of Park et al.
With respect to Claim 4, the combined references make obvious inter alia “wherein the lower contact plug has a first height in a first direction perpendicular to an upper surface of the substrate and a first width in a second direction parallel to the upper surface of the substrate, and wherein a ratio of the first width to the first height ranges from 0.7 to 1.7”, as changes in size are prima facie obvious. See In re Rose, 105 USPQ 237 (CCPA 1955).
With respect to Claim 5, the combined references make obvious the limitation “wherein the lower insulating pattern and the lower contact pattern are on an inner surface of the lower barrier pattern, wherein an upper surface of the lower insulating pattern and a lower surface of the lower contact pattern are in contact with each other; and an upper surface of the lower contact pattern is at a same height as an upper surface of the lower barrier pattern”. See Figure 4 of Park et al; and Figure 9 of Cheng et al.
With respect to Claim 6, the combined references make obvious the limitation “wherein a lower surface of the lower electrode is in contact with an upper surface of the lower contact pattern and an upper surface of the lower barrier pattern”. See Figure 4 of Park et al; and Figure 9 of Cheng et al.
With respect to Claim 7, the combined references make obvious the limitation “ wherein the lower insulating pattern has a height in the first direction perpendicular to an upper surface of the substrate, and wherein the height of the lower insulating pattern is 100 angstroms to 300 angstroms”, as changes in size are prima facie obvious. See In re Rose, 105 USPQ 237 (CCPA 1955).
With respect to Claim 8, the combined references make obvious the limitation “wherein the lower barrier pattern has a first thickness between the lower insulating pattern and the substrate in a first direction perpendicular to an upper surface of the substrate, and wherein the first thickness of the lower barrier pattern is 50 to 150 angstroms”, as changes in size are prima facie obvious. See In re Rose, 105 USPQ 237 (CCPA 1955).
With respect to Claim 9, Park et al discloses further comprising a lower wiring (Figure 4, 130_ between the substrate (Figure 4, 100) and the lower contact plug (Figure 4, 140), wherein the lower wiring is electrically connected to the lower contact plug; and an upper wiring (Figure 4, BL) on the data storage pattern (Figure 4, 150), wherein the upper wiring is electrically connected to the data storage pattern. See Figure 4 of Park et al.
With respect to Claim 10, Park et al disclose wherein the lower wiring (Figure 4, 130) is in contact with a lower surface of the lower barrier pattern (Figure 4, 141).
With respect to Claim 11, Park et al discloses further comprising an etching stop layer (Figure 4, 111b) on the substrate (Figure 4, 100), wherein at least a portion of an outer surface of the lower contact plug (Figure 4, 140) is in contact with the etching stop layer. See Figure 4 of Park et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
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AGG
November 18, 2025
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812