DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 6-8, filed on October 20, 2025, with respect to the rejection(s) of claim(s) 11-20 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of KIM et al. (US 2012/0168899).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0057339) in view of KIM et al. (US 2012/0168899).
Re Claim 11, Lee et al. disclose a method of manufacturing an integrated circuit device, the method comprising: forming multiple conductive layers (230 232 234) on an upper surface of a substrate (210); forming a capping structure (236 238 244 250) arranged on the multiple conductive layers and extending in a first direction (see Fig. 8J); forming a plurality of bit lines (BL, 230B 232B 234B) extending in the first direction by etching the multiple conductive layers using the capping structure (see Fig. 8L), forming a spacer structure (252) opposite sidewalls of each of the plurality of bit lines (see Fig. 8M); and forming a conductive layer (256 260) in a space between neighboring bit lines of the plurality of bit lines (BL), wherein the conductive layer (256) covers an upper portion of each of the plurality of bit lines (BL) and an outer surface of the spacer structure (see Figs. 4A, 8J – 8Q and related text in Paragraphs [0089] – [0099]).
Although Lee et al disclose that forming a conductive layer (256 260) in a space between neighboring bit lines of the plurality of bit lines (BL), wherein the conductive layer (256) covers an upper portion of each of the plurality of bit lines (BL) and an outer surface of the spacer structure, Lee et al. silent about the conductive layer being polysilicon.
KIM et al. disclose forming a polysilicon layer (95, see Paragraph [0123]) in a space between neighboring bit lines of the plurality of bit lines (97), wherein the polysilicon layer (95) covers an upper portion of each of the plurality of bit lines (97) and an outer surface of the spacer structure in order to form a storage node contact (see Fig. 8B and Paragraph [0125]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide Lee reference with polysilicon as taught by KIM et al. in order to form a storage node contact.
Re Claim 12, as applied to claim 11 above, Lee et al, and KIM et al. in combination disclose all the claimed limitations including forming an insulating space by (270S) etching a portion of the polysilicon layer (260), wherein an insulating pattern is filled in the insulating space (see Fig. 8Q).
Re Claim 13, as applied to claim 11 above, Lee et al, and KIM et al. in combination disclose all the claimed limitations including wherein each of the plurality of bit lines comprises a tungsten layer, and wherein an upper surface of the polysilicon layer is at a higher level than an upper surface of the tungsten layer (see Figs. 8J – 8Q and related text in Paragraphs [0089] – [0099]).
Re Claim 14, as applied to claim 11 above, Lee et al, and KIM et al. in combination disclose all the claimed limitations including wherein the polysilicon layer is arranged in the space between neighboring bit lines of the plurality of bit lines in a second direction perpendicular to the first direction (see Figs. 8J – 8Q and related text in Paragraphs [0089] – [0099]).
Re Claim 15, as applied to claim 11 above, Lee et al, and KIM et al. in combination disclose all the claimed limitations including wherein the polysilicon layer comprises a doping ion (see Figs. 8J – 8Q and related text in Paragraphs [0089] – [0099]).
Re Claim 16, as applied to claim 11 above, Lee et al, and KIM et al. in combination disclose all the claimed limitations including wherein at least a portion of the polysilicon layer is electrically connected to a capacitor lower electrode (see Figs. 8J – 8Q and related text in Paragraphs [0046], [0064] and [0089] – [0099]).
Re Claim 17, as applied to claim 11 above, Lee et al, and KIM et al. in combination disclose all the claimed limitations including wherein at least a portion of the polysilicon layer is electrically connected to the substrate see Figs. 8J – 8Q and related text in Paragraphs [0046], [0064] and [0089] – [0099]).
Re Claim 18, as applied to claim 11 above, Lee et al, and KIM et al. in combination disclose all the claimed limitations including forming at least one peripheral circuit gate structure on the substrate; and forming a polysilicon layer on the at least one peripheral circuit gate structure, wherein the forming of the polysilicon layer on the at least one peripheral circuit gate structure comprises forming the polysilicon layer to cover an entire upper surface of the at least one peripheral circuit gate structure see Figs. 8J – 8Q and related text in Paragraphs [0046], [0064] and [0089] – [0099]).
Re Claim 19, Lee et al. disclose a method of manufacturing an integrated circuit device, the method comprising: forming multiple conductive layers (230 232 234) on an upper surface of a substrate (210); forming a capping structure (236 238 244 250) arranged on the multiple conductive layers (230 232 234) and extending in a first direction (see Fig. 8J); forming a plurality of bit lines (BL, 2302 232B 234B) extending in the first direction by etching the multiple conductive layers using the capping structure (see Fig 8L); forming a spacer structure (252) on opposite sidewalls of each of the plurality of bit lines (see Fig. 8M); forming a polysilicon layer (256 260) in a space between neighboring bit lines of the plurality of bit lines (see Fig. 8); and forming an insulating space (270S) by etching a portion of the polysilicon layer (see Fig. 8Q), wherein each of the plurality of bit lines comprises a tungsten layer (see Paragraph [0037]), and an upper surface of the polysilicon layer is at a higher level than an upper surface of the tungsten layer (see Fig. 8Q), wherein the conductive layer comprises doping ions and is arranged in a space between neighboring bit lines of the plurality of bit lines in a second direction perpendicular to the first direction, an upper end of the conductive layer is connected to a lower electrode of a capacitor formed on the plurality of bit lines (see Paragraph [0030]), and a lower end of the polysilicon layer is connected to the substrate (see Figs. 4A, 8J – 8Q and related text in Paragraphs [0089] – [0099]).
Although Lee et al disclose that forming a conductive layer (256 260) in a space between neighboring bit lines of the plurality of bit lines (BL), wherein the conductive layer (256) covers an upper portion of each of the plurality of bit lines (BL) and an outer surface of the spacer structure, Lee et al. silent about the conductive layer being polysilicon.
KIM et al. disclose forming a polysilicon layer (95, see Paragraph [0123]) in a space between neighboring bit lines of the plurality of bit lines (97), wherein the polysilicon layer (95) covers an upper portion of each of the plurality of bit lines (97) and an outer surface of the spacer structure in order to form a storage node contact (see Fig. 8B and Paragraph [0125]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide Lee reference with polysilicon as taught by KIM et al. in order to form a storage node contact.
Re Claim 20, as applied to claim 19 above, Lee et al, and KIM et al. in combination disclose all the claimed limitations including forming at least one peripheral circuit gate structure on the substrate; and forming a polysilicon layer on the at least one peripheral circuit gate structure, wherein the forming of the polysilicon layer on the at least one peripheral circuit gate structure comprises forming the polysilicon layer to cover an entire upper surface of the at least one peripheral circuit gate structure (see Figs. 4A, 8J – 8Q and related text in Paragraphs [0089] – [0099]).
Allowable Subject Matter
Claims 1-10 are allowed over prior art of record.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “wherein the capping structure comprises a lower insulating capping layer disposed directly on an uppermost layer of the multiple conductive layers, an insulating layer disposed directly on the lower insulating capping layer, and a polysilicon layer disposed directly on the insulating layer,” as recited in claim 1.
Claims 2-10 are also allowed as being directly or indirectly dependent of the allowed independent base claim.
Conclusion
THIS ACTION IS MADE NON-FINAL.
Correspondence
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/BROOK KEBEDE/
Primary Examiner, Art Unit 2894
/BK/
January 23, 2026