Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/19/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 12-13 and 15-18, 20 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by GUILLORN (Pub. No.: US 2018/0006159).
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Re claim 1, GUILLORN, Fig. 15A teaches a field effect transistor (FET) device comprising:
a first channel [FC] over a first region [FR] of a substrate (202);
a second channel [SC] over a second region [SR] of the substrate and adjacent to the first channel region;
a first junction formed by the first channel [FC] and a shared S/D (middle 238);
a second junction formed by the second channel [SC] and the shared S/D; and
a bottom conductive metal layer (middle 242) over a third region [TR] of the substrate and configured to form a bottommost component of a multi-component wrap-around source or drain (S/D) contact;
wherein the shared S/D (middle 238) is distinct from the bottom conductive metal layer (middle 242);
wherein the first region [FR] of the substrate, the second region [SR] of the substrate, and the third region [TR] of the substrate do not overlap; and
wherein the shared S/D region (middle 238) of the FET device is electronically coupled to the bottom conductive metal layer (middle 242) at an interface comprising a top surface of the bottom conductive metal layer (middle 242) and a bottom surface of the shared S/D (middle 238) of the FET device.
Re claim 12, GUILLORN, Fig. 15A teaches the device of claim 1, wherein the bottom conductive metal layer is selected from a group consisting of tungsten, ruthenium, an alloy of an elemental metal, a metal nitride (middle 242, [0122]), a metal silicide, and combinations thereof.
Re claim 13, GUILLORN, Fig. 15A teaches a field effect transistor (FET) device comprising:
a first channel region [FC] over a first region [FR] of a substrate (202);
a second channel region [SC] over a second region [SR] of the substrate and adjacent to the first channel region;
a first junction formed by the first channel [FC] and a shared S/D region [aS/D];
a second junction formed by the second channel [SC] and the shared S/D region; and
a bottom conductive metal layer (242, [0122]) over a third region [TR] of the substrate and configured to form a bottommost component of a multi-component wrap-around source or drain (S/D) contact;
wherein the shared S/D region ([aS/D]/middle 238) is distinct from the bottom conductive metal layer;
wherein the first region [FR] of the substrate, the second region [SR] of the substrate, and the third region [TR] of the substrate do not overlap;
wherein the shared S/D region [aS/D] of the FET device is electronically coupled to the bottom conductive metal layer (242) at an interface [I] comprising a top surface of the bottom conductive metal layer (middle 242) and a bottom surface of the shared S/D region (middle 238) of the FET device; and
a top S/D contact region (240) over the shared S/D region and configured to form an upper component of the multi-component wrap-around S/D contact;
wherein the top S/D contact region (middle 240) is electronically coupled to the bottom conductive metal layer such that the top S/D contact region coupled to the bottom conductive metal layer (middle 242) defines a central opening; and
wherein the central opening is occupied by the shared S/D region (middle 238).
Re claim 15, GUILLORN, Fig. 15A teaches the device of claim 13, wherein:
the bottom conductive metal layer comprises a first conductive material (middle 242); the top S/D contact region comprises a second conductive material (middle 239); and the first conductive material (middle 242) is different than the second conductive material.
Re claim 16, GUILLORN, Fig. 15A teaches the device of claim 13, wherein a surface area of an interface [I] between the wrap-around S/D contact and the shared S/D region comprises:
a first surface area of an interface between the shared S/D region (middle 238) and a first portion of the top surface of the bottom conductive metal layer (middle 242); and
a second surface area of an interface between the top S/D contact region (middle 239) and the shared S/D region (middle 238).
Re claim 17, GUILLORN, Fig. 15A teaches the device of claim 13, wherein the shared S/D region (middle 238) is electronically coupled to the bottom conductive metal layer (middle 242) through a first region of the top surface of the bottom conductive metal layer.
Re claim 18, GUILLORN, Fig. 15A teaches the device of claim 17, wherein the top S/D contact region (middle 239) is electronically coupled to the bottom conductive metal layer (middle 242) through a second region of the top surface of the bottom conductive metal layer (sidewalls of middle 242).
Re claim 20, GUILLORN, Fig. 15A teaches the device of claim 13, wherein: the top S/D contact region comprises:
a contact liner (middle 238);
a barrier liner (middle 238); and 9
a conductive metal (middle 240).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guba (Pub. No.: US 2020/0044087) in view of TAPILY (Pub. No.: US 2018/0047832).
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Re claim 1, Guba, FIG. 1 [as shown above] teaches a field effect transistor (FET) device comprising:
a first channel [FC] over a first region of a substrate [FR];
a second channel [SC] over a second region [SR] of the substrate and adjacent to the first channel [FC];
a first junction formed by the first channel [FC] and a shared S/D [aS/D];
a second junction [SC] formed by the second channel and the shared S/D [aS/D];
a bottom conductive layer [BCL] over a third region [TR] of the substrate and configure to form a bottommost component of a multi-component wrap-around source or drain (S/D) contact;
wherein the shared S/D [aS/D] is distinct from the bottom conductive metal layer [BCL];
wherein the first region [FR] of the substrate, the second region [SR] of the substrate, and the third region [TR] of the substrate do not overlap; and
wherein the shared S/D [aS/D] of the FET device is electronically coupled to the bottom conductive layer [BCL] at an interface [I] comprising a top surface of the bottom conductive layer [BCL] and a bottom surface of the shared S/D region [aS/D] of the FET device
Guba fails to teach the bottom conductive metal layer.
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TAPILY teaches the bottom conductive metal layer (130, FIG. 2 [as shown above], ¶ [0036]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the flexibility of manufacturing process as taught by TAPILY. [0004].
Re claim 12, in the combination, TAPILY, FIG. 2 teaches the device of claim 1, wherein the bottom conductive metal layer (S/D metal 130, [0036]).
TAPILY differs from the invention by not showing wherein the bottom conductive metal layer is selected from a group consisting of tungsten, ruthenium, an alloy of an elemental metal, a metal nitride, a metal silicide, and combinations thereof.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the above said teaching since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Re claim 13, Guba, FIG. 1 [as shown above] teaches a field effect transistor (FET) device comprising:
a first channel region [FC] over a first region [FR] of a substrate (100);
a second channel region [SC] over a second region [SR] of the substrate and adjacent to the first channel region;
a first junction formed by the first channel [FC] and a shared S/D region [aS/D];
a second junction formed by the second channel [SC] and the shared S/D region; and
a bottom conductive layer [BCL] over a third region [TR] of the substrate and configured to form a bottommost component of a multi-component wrap-around source or drain (S/D) contact;
wherein the shared S/D region [aS/D] is distinct from the bottom conductive metal layer;
wherein the first region [FR] of the substrate, the second region [SR] of the substrate, and the third region [TR] of the substrate do not overlap;
wherein the shared S/D region [aS/D] of the FET device is electronically coupled to the bottom conductive layer [BCL] at an interface [I] comprising a top surface of the bottom conductive layer (middle 242) and a bottom surface of the shared S/D region [aS/D] of the FET device; and
wherein the central opening is occupied by the shared S/D region [aS/D].
Guba fails to teach the bottom conductive metal layer; and a top S/D contact region over the shared S/D region and configured to form an upper component of the multi-component wrap-around S/D contact; wherein the top S/D contact region is electronically coupled to the bottom conductive metal layer.
TAPILY teaches the bottom conductive metal layer ([BCL/bottom 130, FIG. 2 [as shown above], ¶ [0036]); and
a top S/D contact region (T[S/D]) over the shared S/D region [aS/D] and configured to form an upper component of the multi-component wrap-around S/D contact;
wherein the top S/D contact region (T[S/D]) is electronically coupled to the bottom conductive metal layer [BCL].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the flexibility of manufacturing process as taught by TAPILY. [0004].
Moreover, after the combining of Guba and TAPILY would teach wherein the top S/D contact region is electronically coupled to the bottom conductive metal layer such that the top S/D contact region coupled to the bottom conductive metal layer defines a central opening.
Response to Arguments
Applicant's arguments with respect to claim 1 on the remarks filed on 02/16/2026 have been considered but are not persuasive
In response to Applicant’s argument:
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The Examiner respectfully submits that Guba, FIG. 1 [as shown above] teaches bottom conductive metal layer [BCL] beneath a shared S/D (aS/D) and required interface [I].
TAPILY, FIG. 2 [as shown above] teaches shared S/D [aS/D] distinct from bottom metal ([BCL]/bottom 130).
Both Guba, FIG. 1 and TAPILY, FIG. 2 [as shown above] teaches multi-component wrap-around contact geometry.
For the above reasons, it is believed that the rejections should be sustained.
Allowable Subject Matter
Claims 2-10 and 14, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
In the claim 2 that is written, the prior arts fail to show or fairly suggest: “the first section tapers downward toward the first channel region and the second section tapers downward toward the second channel region such that:
portions of the bottom conductive metal layer that are closest to the first channel region do not contact a first sidewall of the first channel region; and portions of the bottom conductive metal layer that are closest to the second channel region do not contact a first sidewall of the second channel” in context with the other limitation as stated in claims 1-2.
In the claim 10 that is written, the prior arts fail to show or fairly suggest: “wherein a non-uniform height of the bottom conductive metal layer tapers downward for portions of the bottom conductive metal layer that are closest to the first channel stack; wherein the non-uniform height of the bottom conductive metal layer tapers downward for portions of the bottom conductive metal layer that are closest to the second channel stack” in context with the other limitation as stated in claim 10.
In the claim 14 that is written, the prior arts fail to show or fairly suggest: “the first section tapers downward toward the first channel region and the second section tapers downward toward the second channel region such that: portions of the bottom conductive metal layer that are closest to the first channel region do not contact a first sidewall of the first channel region; and portions of the bottom conductive metal layer that are closest to the second channel region do not contact a first sidewall of the second channel region” in context with the other limitation as stated in claims 13-14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached on Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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