SEMICONDUCTOR PACKAGE INCLUDING BUMP INTERCONNECTION STRUCTURE

Application No. 18/308,891

• Filed: Apr 28, 2023
• Priority: Nov 10, 2022 — RE 10-2022-0149834
• Examiner: HANUMASAGAR, SHAMITA S
• Art Unit: 2814
• Tech Center: 2800 — Semiconductors & Electrical Systems
• Assignee: SK hynix Inc.
• OA Round: 3 (Final)

Office Action

Attorney Docket Number: PA5329-0
Filing Date: 04/28/2023
Claimed Priority Date: 11/10/2022 (KR 10-2022-0149834)
Inventors: Kim et al.
Examiner: Shamita S. Hanumasagar

DETAILED ACTION
This Office action responds to the amendment filed on 01/28/2026.
Initial Remarks
The “final rejection” mailed on 06/09/2026 is hereby overwritten and may be disregarded. The previous final rejection was inadvertently and erroneously prematurely mailed due to a clerical error and is therefore of no effect. Subsequently, a second corrective final rejection is issued in this Office action to overwrite the final rejection that was mailed on 06/09/2026 to correct the recited errors in the previously mailed Office action.
Accordingly, the present final rejection provided corrects the errors and is properly directed to the present application. Accordingly, the prior communication is of no effect and the present final rejection provided below entirely replaces the previous final rejection correspondence.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 01/28/2026 in reply to the previous Office action mailed on 10/28/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1 and 3-21, with claims 6-20 remaining withdrawn from consideration.
Reference Remarks
Regarding all citations from all non-U.S. references, please refer to the original non-English versions of the documents, which are attached to this Office action and to the previous Office action mailed on 10/28/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3-5, and 21 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites the limitation “a bump disposed to face the first lead below a second substrate”. The language of the claim does not clearly distinguish whether the “bump” is intended to be below a second substrate or whether the “first lead” is intended to be below a second substrate. Accordingly, this limitation in the claim is indefinite. For the express purposes of examination, the limitation “a bump disposed to face the first lead below a second substrate” is construed as “a bump disposed to face the first lead, wherein the bump is below a second substrate”.
Claims 3-5 and 21 depend from claim 1 and thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yan (CN 113990834A).

Regarding claim 1, Yan (see, e.g., fig. 3) shows all aspects of the instant invention, including a semiconductor package (see, e.g., par.0037) comprising:
a first lead (leftmost 110/130) and a second lead (rightmost 110/130) spaced apart from each other on a first substrate 100;
a bump 210 disposed to face the first lead, wherein the bump is below a second substrate 200; and
a solder layer 400 configured to connect the bump and the first lead;
wherein:
the first lead (leftmost 110/130) has a stair shape that ascends toward the second lead (rightmost 110/130) (see, e.g., the orientation of the protruding portion 130 of Yan’s first lead when viewed coming from the left);
the first lead (leftmost 110/130) comprises a first part 110 and a second part 130, the second part of the first lead leaves a part of the first part of the first lead exposed (leftmost portion of 110 exposed from 130 and to the left of 130), and the second part of the first lead has a higher surface height from the first substrate 100 toward the second substrate 200 than the exposed part of the first part of the first lead; and
the second part of the first lead is positioned on one edge (e.g., an uppermost edge) of the first part of the first lead
With regards to other language recited in claim 1, see the comments stated above in paragraph 8.
Regarding claim 3, Yan (see, e.g., fig. 3) shows that the second part 130 of the first lead (leftmost 110/130) protrudes from the first part 110 of the first lead toward the second substrate 200.
Regarding claim 4, Yan (see, e.g., fig. 3) shows that the second part 130 of the first lead (leftmost 110/130) is closer to the second lead (rightmost 110/130) than the exposed part (leftmost portion of 110 exposed from 130 and to the left of 130) of the first part 110 of the first lead (leftmost portion of 110 exposed from 130 and to the left of 130).
Regarding claim 5, Yan (see, e.g., fig. 3) shows that the second lead (rightmost 110/130) has a stair shape that ascends toward the first lead (leftmost 110/130) (see, e.g., the orientation of the protruding portion 130 of Yan’s second lead when viewed coming from the right).
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai (US 2010/0163292).

Regarding claim 1, Tsai (see, e.g., fig. 10A) shows all aspects of the instant invention, including a semiconductor package 200 comprising:
a first lead 214A/220A and a second lead 214B/220B spaced apart from each other on a first substrate 210;
a bump 240A disposed to face the first lead, wherein the bump is below a second substrate 230;
a solder layer 250A (see, e.g., par.0044/ll.4) configured to connect the bump and the first lead;
wherein:
the first lead 214A/220A has a stair shape that ascends toward the second lead 214B/220B;
the first lead comprises a first part 214A and a second part 220A, the second part 220A of the first lead leaves a part of the first part of the first lead exposed, and the second part of the first lead has a higher surface height from the first substrate 210 toward the second substrate 230 than the exposed part of the first part of the first lead (see, e.g., fig. 10A); and
the second part of the first lead is positioned on one edge of the first part of the first lead (see, e.g., fig. 10A)
With regards to other language recited in claim 1, see the comments stated above in paragraph 8.
Regarding claim 3, Tsai (see, e.g., fig. 10A) shows that the second part 220A of the first lead 214A/220A protrudes from the first part 214A of the first lead toward the second substrate 230.
Regarding claim 4, Tsai (see, e.g., fig. 10A) shows that the second part 220A of the first lead 214A/220A is closer to the second lead 214B/220B than the exposed part of the first part 214A of the first lead.
Regarding claim 5, Tsai (see, e.g., fig. 10A) shows that the second lead 214B/220B has a stair shape that ascends toward the first lead 214A/220A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai.
Regarding claim 21, Tsai shows the instant invention (see paragraph 18 above). Tsai (see, e.g., fig. 10A) further shows that the second part 220A of the first lead 214A/220A is positioned closer to the second lead 214B/220B than any of the exposed part of the first part 214A of the first lead, and induces solder material of the solder layer 250A to extrude in a direction opposite to the second lead (see the comments stated below in paragraphs 26-29 regarding this limitation).
In reference to the claim language pertaining to “induc[ing] solder material of the solder layer to extrude in a direction opposite to the second lead”, the claiming of a new use, new function, or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. (In re Best, 195 USPQ 430, 433 (CCPA 1977) and In re Swinehart, 439 F. 2d 210, 169 USPQ 226 (CCPA 1971); please see MPEP § 2112). Since Tsai shows all the features of the claimed invention, the characteristic of “inducing solder material of the solder layer to extrude in a direction opposite to the second lead” are an inherent property of Tsai’s invention.
That is, the specific claim limitation that the second part of the first lead induces solder material of the solder layer to extrude in a direction opposite to the second lead is a property of the first lead of Tsai’s device.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the instant case, Tsai teaches the same second part of the first lead as positioned closer to the second lead than any of the exposed part of the first part of the first lead as recited in the claim, therefore, the second part of the first lead will have the solder inducement properties also recited in the claim.
Claims 1, 3-5, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiura (US 2005/0056458) in view of Guevara (US 2022/0320038).
Regarding claim 1, Sugiura (see, e.g., fig. 6 and pars.0071-0072) shows most aspects of the instant invention, including a semiconductor package comprising:
a first lead 31 and a second lead 33 spaced apart from each other on a first substrate 35;
a second substrate 37, wherein the first lead is below the second substrate; and
a solder layer 39 configured to connect the second substrate and the first lead;
wherein:
the first lead 31 has a stair shape that ascends toward the second lead 33;
the first lead comprises a first part (long rectangular portion of 31 closest to 35) and a second part (short rectangular portion of 31 closest to 37), the second part of the first lead leaves a part of the first part of the first lead exposed, and the second part of the first lead has a higher surface height from the first substrate 35 toward the second substrate 37 than the exposed part of the first part of the first lead; and
the second part of the first lead is positioned on one edge of the first part of the first lead (see, e.g., fig. 6)
Although Sugiura shows most aspects of the instant invention, Sugiura fails to specify a bump disposed to face the first lead, wherein the bump is disposed below the second substrate, and that the solder layer is configured to connect the bump and the first lead. Guevara, in the same field of endeavor and in a similar device to Sugiura, teaches that having a bump disposed below a second substrate provides a low resistance path between vertically-aligned substrates and can aid in the transferring of thermal energy out of semiconductor packages (see, e.g., Guevara: par.0018/ll.17-23). Guevara further teaches that the inclusion of such bumps allows for the movement of varying signals, such as power terminals/high current signals and control or logic signals, which can be modulated as desired according to package requirements (see, e.g., Guevara: par.0018/ll.35-38). Additionally, Guevara teaches that bumps may be manufactured such that when a bump is disposed to face a first lead such that a solder layer connects the bump and the first lead, improved alignment and reliable solder joint formation can be ensured (see, e.g., Guevara: par.0035/ll.34-36).
Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have in Sugiura’s device a bump disposed to face the first lead, wherein the bump is disposed below the second substrate, and to have the solder layer is configured to connect the bump and the first lead, as taught by Guevara, so as to provide a low resistance path between Sugiura’s vertically-aligned substrates and aid in the transferring of thermal energy out of Sugiura’s semiconductor package whilst simultaneously allowing for the movement of varying signals, such as power terminals/high current signals and control or logic signals, to be modulated as desired according to package requirements, and so as to ensure improved alignment and reliable solder joint formation in Sugiura’s device.
With regards to other language recited in claim 1, see the comments stated above in paragraph 8.
Regarding claim 3, Sugiura (see, e.g., fig. 6 and pars.0071-0072) shows that the second part (short rectangular portion of 31 closest to 37) of the first lead 31 protrudes from the first part (long rectangular portion of 31 closest to 35) of the first lead toward the second substrate 37.
Regarding claim 4, Sugiura (see, e.g., fig. 6 and pars.0071-0072) shows that the second part (short rectangular portion of 31 closest to 37) of the first lead 31 is closer to the second lead 33 than the exposed part of the first part (long rectangular portion of 31 closest to 35) of the first lead.
Regarding claim 5, Sugiura (see, e.g., fig. 6 and pars.0071-0072) shows that the second lead 33 has a stair shape that ascends toward the first lead 31.
Regarding claim 21, Sugiura (see, e.g., fig. 6 and par.0072/ll.7-12) shows that the second part (short rectangular portion of 31 closest to 37) of the first lead 31 is positioned closer to the second lead 33 than any of the exposed part of the first part (long rectangular portion of 31 closest to 35) of the first lead, and induces solder material of the solder layer 39 to extrude in a direction opposite to the second lead.
Response to Arguments
Applicant’s amendments to the claims have overcome the objections to the drawings put forth in the previous Office action mailed on 10/28/2025. Accordingly, the objections to the drawings as put forth in the previous Office action are hereby withdrawn.
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is [phone]. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at [phone] and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via [e-mail]. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on [phone].
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814

Prosecution Timeline

• Apr 28, 2023: Application Filed
• Oct 28, 2025: Non-Final Rejection mailed — §102, §103, §112
• Jan 28, 2026: Response Filed
• Jun 09, 2026: Final Rejection mailed — §102, §103, §112
• Jun 16, 2026: Final Rejection mailed — §102, §103, §112 (current)