DETAILED ACTION
This Office Action is in response to Amendment filed December 26, 2025.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 9, 12 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ozaki et al. (US 2022/0069112) in view of Sani et al. (“Improving Thermal Effects and Reduction of Self-heating Phenomenon in AlGaN/GaN/Si Based HEMT,” Journal of ELECTRONIC MATERIALS (2021))
Regarding claim 1, Ozaki et al. disclose a semiconductor device (Fig. 1) comprising: a substrate (901); a semiconductor layer (one or more layer of semiconductor laminated structure 907) ([0032]) provided on the substrate; a source electrode (913) ([0033]) and a drain electrode (914), the source electrode and the drain electrode being provided on the semiconductor layer; (a portion of) a first film (film including 921) ([0033]) including a first insulating film (921) that is provided on the semiconductor layer (one or more layer of semiconductor laminated structure 907) and is located between the source electrode and the drain electrode, the first film having an opening (920) ([0033]); a gate electrode (930) ([0033]) provided between the source electrode (913) and the drain electrode (914), the gate electrode including a first portion (middle portion of gate electrode 930) that is located within the opening in a plan view, and a second portion (right portion of gate electrode 930) that is connected to the first portion, is disposed on the first film (film including 921), and is located closer to the drain electrode than the first portion (middle portion of gate electrode 930) is.
Ozaki et al. differ from the claimed inventio by not comprising a silicon carbide layer covering the first portion and the second portion of the gate electrode and the first film.
Sani et al. disclose a semiconductor device (Fig. 8), comprising a silicon carbide layer (6H-SiC Passive layer) covering top and side surfaces of a gate electrode (Gate) and a remaining portion of the underlying structure.
Since both Ozaki et al. and Sani et al. teach a semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor device disclosed by Ozaki et al. can further comprise a silicon carbide layer covering the first portion and the second portion of the gate electrode and the first film as suggested by Sani et al., because (a) Ozaki et al. and Sani et al. disclose very similar semiconductor device structures including a silicon carbide substrate and GaN cap layer, (b) Sani et al. disclose in second paragraph under SIMULATION RESULTS on page 5 that “Because of the high thermal conductivity of the SiC material, the device transmits the temperature from the inside to the outside at high voltage and high temperature, which also increases the breakdown voltage of the device”, (b) therefore, either the passivation film 921 disclosed by Ozaki et al. can be formed of silicon carbide followed by forming the opening 920 and the gate electrode 930 in Ozaki et al. followed by deposition of the 6H-SiC Passive layer disclosed by Sani et al., or the 6H-SiC Passive layer disclosed by Sani et al. can be deposited on the underlying device structure disclosed by Ozaki et al. as illustrated below to improve thermal conductivity and breakdown voltage of the semiconductor device disclosed by Ozaki et al.,
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and (c) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416.
Regarding claim 6, Ozaki et al. further disclose that the first insulating film (921) is a silicon nitride film ([0033]).
Regarding claim 9, Ozaki et al. in view of Sani et al. further disclose for the semiconductor device according to claim 1 that the silicon carbide layer (6H-SiC of Sani et al.) directly contacts the gate electrode (930 in Fig. 1 of Ozaki et al.).
Regarding claim 12, Ozaki et al. further disclose for the semiconductor device according to claim 1 that a distance between the semiconductor layer (one layer of semiconductor laminated structure 907) and the second portion (right portion of 930) is 100 nm or less, because (a) the topmost semiconductor layer of the semiconductor laminated structure 907, which is the n-GaN cap layer 906, can be referred to as “the semiconductor layer”, and (b) then the claimed distance would correspond to the thickness of the SiN passivation film 921, which is 10 nm to 100 nm ([0041]).
Regarding claim 15, Ozaki et al. further disclose for the semiconductor device according to claim 1 the gate electrode (930) further includes a third portion (left portion of gate electrode 930) that is connected to the first portion (middle portion of gate electrode 930), is disposed on the first film (film including 921), and is located closer to the source electrode (913) than the first portion is.
Regarding claim 16, Ozaki et al. in view of Sani et al. differ from the claimed invention by not showing that the second portion has a slope extending from a top side of the second portion toward a surface of the first film, and wherein the third portion has a slope extending from a top side of the third portion toward the surface of the first film.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second portion can have a slope extending from a top side of the second portion toward a surface of the first film, and the third portion can have a slope extending from a top side of the third portion toward the surface of the first film, because a sloped gate electrode or a sloped T-gate has been commonly employed in manufacturing a HEMT device to control and optimize electric field applied to the channel region since the wing parts of the sloped T-gate would be able to function as field plates, and also to control and optimize the electrical characteristics of the semiconductor device including a threshold voltage.
Regarding claim 17, Ozaki et al. in view of Sani et al. differ from the claimed invention by not showing that the gate electrode includes a nickel film and a gold film.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the gate electrode can include a nickel film and a gold film, because (a) a gate electrode including a nickel film and a gold film are not exactly directed to Applicant’s main inventive concept, (b) a stacked gate electrode structure including a nickel film and a gold film have been commonly employed due to their high electrical conductivity and compatibility with the GaN-based semiconductor materials, and ease of deposition processes, and (c) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ozaki et al. (US 2022/0069112) in view of Sani et al. (“Improving Thermal Effects and Reduction of Self-heating Phenomenon in AlGaN/GaN/Si Based HEMT,” Journal of ELECTRONIC MATERIALS (2021)) and further in view of Hao et al. (WO 2022/126571) The teachings of Ozaki et al. in view of Sani et al. are discussed above.
Regarding claim 10, Ozaki et al. in view of Sani et al. differ from the claimed invention by not further comprising: a first metal layer including the source electrode; and a second metal layer including the drain electrode, wherein the silicon carbide layer directly contacts at least one of the first metal layer or the second metal layer.
Hao et al. disclose a semiconductor device (Fig. 7), comprising a first metal layer (composite layer of 152 and 130 or composite layer of 152 and 136) ([0076] and [0089]) including the source electrode (one of 130 or 136, which corresponds to 913 of Ozaki et al.); and a second metal layer (composite layer of 152 and 136 or composite layer of 152 and 130) including the drain electrode (the other of 130 and 136, which corresponds to 914 of Ozaki et al.).
Since both Ozaki et al. and Hao et al. teach a semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor device disclosed by Ozaki et al. in view of Sani et al. can further comprise: a first metal layer including the source electrode; and a second metal layer including the drain electrode, wherein the silicon carbide layer directly contacts at least one of the first metal layer or the second metal layer as disclosed by Hao et al., because (a) a source and drain electrode, and vias have been commonly formed of a metal to improve an ohmic contact, (b) even though the source electrode 913 and the drain electrode 914 of Ozaki et al. are shown to be covered with the (SiN) passivation film 921 in Fig. 1 of Ozaki et al., the source and drain electrode of Ozaki et al. should be electrically connected to the outside world to be able to function as a semiconductor device, and (c) in this case, vias similar to those vias 152 shown in Fig. 7 of Hao et al. can be formed to be in contact with the source and drain electrode of Ozaki et al. In this case, the silicon carbide layer disclosed by Ozaki et al. in view of Sani et al. would directly contact at least one of the first metal layer or the second metal layer, especially the vias similar to those vias 152 shown in Fig. 7 of Hao et al.
Regarding claim 11, Ozaki et al. in view of Sani et al. and further in view of Hao et al. differ from the claimed invention by not showing that a distance between the gate electrode and the first metal layer is 5 µm or less, and a distance between the gate electrode and the second metal layer is 5 µm or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a distance between the gate electrode and the first metal layer can be 5 µm or less, and a distance between the gate electrode and the second metal layer can be 5 µm or less, because (a) the claimed distances would correspond to distances between the gate electrode and the source/drain electrode or between the gate electrode and the vias, (b) therefore, the distances shown in Fig. 1 of Ozaki et al. or Fig. 7 of Hao et al. can respectively be in the claimed range since the distances should be controlled and optimized to obtain desired overall semiconductor device sizes, and also to control and optimize the electrical characteristics of the semiconductor device including an electric field distribution, a threshold voltage and a switching speed, (c) furthermore, the claimed distances would be met as semiconductor device sizes shrink over time.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US 8,860,089)
Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 February 24, 2026