Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 4, 6, and 16-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/23/2025.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/28/2023 and 1/14/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7-9, 11-15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20220052009 A1) in view of Lin (US 20220302011 A1).
Regarding claim 1, Huang discloses a semiconductor package (Fig. 14) comprising:
a first semiconductor chip (170) comprising a first top surface (See annotated figure) and an opposite first bottom surface (See annotated figure);
a plurality of first pads (204A, an encircled grouping, See annotated figure. Note: the examiner is interpreting the structures of Huang as “pads”, consistent with the “pads” in Fig. 3 of Applicant’s disclosure) on the first top surface, each of the plurality of first pads having a first width (horizontal width. See annotated figure for direction designation) and a first height (vertical height);
a plurality of second pads (204A, an encircled grouping, See annotated figure) on the first top surface further outward (horizontally outward) from a center of the first semiconductor chip than the plurality of first pads, each of the plurality of second pads having a second width (horizontal width) […] and a second height (vertical height) greater than the first height (shown by exaggerated heights in the figure; [0063]: “varying heights to account for the warpage and/or curve of the die”);
and a second semiconductor chip (100) comprising a second bottom surface (See annotated figure) which faces the first top surface, and an opposite second top surface (See annotated figure), a plurality of third pads (202, an encircled grouping, See annotated figure) on the second bottom surface and connected to the plurality of first pads, and a plurality of fourth pads (202, an encircled grouping, See annotated figure) on the second bottom surface and connected to the plurality of second pads, wherein the second bottom surface is convex (a convex shape is shown).
Illustrated below is a marked and annotated figure of Fig. 14 of Huang.
PNG
media_image1.png
405
733
media_image1.png
Greyscale
Huang fails to teach “each of the plurality of second pads having a second width less than the first width”.
Lin discloses a plurality of first pads (Fig. 1I: MP1) on the first top surface, each of the plurality of first pads having a first width (W1, See Fig. 1G for measurement markings) and a first height (See dashed reference line in annotated figure); a plurality of second pads (MP2) on the first top surface further outward from a center of the first semiconductor chip (AR1) than the plurality of first pads (See Fig. 1G showing 118B/MP2 “further outward”), each of the plurality of second pads having a second width (W2, See Fig. 1G for measurement markings) less than the first width ([0033]: “width W1…is greater than…width W2”) and a second height (See dashed reference line in annotated figure) greater than the first height (greater height is shown).
Modifying the first and second widths of Huang by including the width configuration of Lin would arrive at the claimed widths. Lin provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the width configuration in that it would improve package reliability by improving connections to the pads ([0046]: “the warpage problem may be compensated and the cold joint problem may be prevented”). A person of ordinary skill in the art before the effective filing date would have predictable results incorporating the width configuration because in Huang and Lin each teach pad dimensions are designed according to chip warpage (Huang: [0011]: “variable heights to account for any warpage”; Lin: [0046]: “By designing the heights and widths”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed width configuration because it would improve package reliability.
Illustrated below is a marked and annotated figure of Fig. 1I of Lin.
PNG
media_image2.png
382
516
media_image2.png
Greyscale
Regarding claim 2, Huang in view of Lin discloses the semiconductor package of claim 1 (Huang: Fig. 14), wherein a distance between the plurality of first pads and the plurality of third pads (vertical distance, See annotated figure) is the same as a distance between the plurality of second pads and the plurality of fourth pads (vertical distance. “same” appears to be illustrated and there is no disclosure to the contrary).
Regarding claim 3, Huang in view of Lin discloses the semiconductor package of claim 1 (Huang: Fig. 14), wherein a width of each of the plurality of third pads is the same as a width of each of the plurality of fourth pads (The figure shows horizontal pad dimensions of the first chip match horizontal pad dimensions of the second chip. This matching is retained when incorporating the width modification of Lin).
Regarding claim 5, Huang in view of Lin discloses the semiconductor package of claim 1 (Huang: Fig. 14), further comprising: a plurality of first bumps (some of 206A) between the plurality of first pads and the plurality of third pads; and a plurality of second bumps (others of 206A) between the second pads and the fourth pads.
Regarding claim 7, Huang in view of Lin discloses the semiconductor package of claim 1 (Huang: Fig. 14), wherein a distance between the second bottom surface and the plurality of first pads (vertical distance, See annotated figure) is the same as a distance between the second bottom surface and the plurality of second pads (vertical distance. “same” appears to be illustrated and there is no disclosure to the contrary).
Regarding claim 8, Huang in view of Lin discloses the semiconductor package of claim 1 (Huang: Fig. 26), further comprising: a fillet layer (210) between the first and second semiconductor chips (vertically between) and surrounding the plurality of first pads, the plurality of second pads, the plurality of third pads, and the plurality of fourth pads (horizontally surrounding).
Illustrated below is a marked and annotated figure of Fig. 26 of Huang.
PNG
media_image3.png
406
726
media_image3.png
Greyscale
Regarding claim 9, Huang in view of Lin discloses the semiconductor package of claim 1 (Huang: Fig. 26), wherein the first semiconductor chip comprises a substrate (172) and a plurality of through electrodes (174) that extend through the substrate (vertically through) and are connected to the plurality of first pads and the plurality of second pads (electrically connected).
Regarding independent claim 11, Huang discloses a semiconductor package (Fig. 14) comprising:
a first semiconductor chip (170) comprising a first top surface (See annotated figure) and an opposite first bottom surface (See annotated figure);
a plurality of first pads (204A, an encircled grouping, See annotated figure. Note: the examiner is interpreting the structures of Huang as “pads”, consistent with the “pads” in Fig. 3 of Applicant’s disclosure) on the first top surface, each of the plurality of first pads having a first width (horizontal width. See annotated figure for direction designation) and a first height (vertical height);
a plurality of second pads (204A, an encircled grouping, See annotated figure) on the first top surface further outward (horizontally outward) from a center of the first semiconductor chip than the plurality of first pads, each of the plurality of second pads having a second width (horizontal width) […] and a second height (vertical height) greater than the first height (shown by exaggerated heights in the figure; [0063]: “varying heights to account for the warpage and/or curve of the die”);
a second semiconductor chip (100) comprising a second bottom surface (See annotated figure) which faces the first top surface, an opposite second top surface (See annotated figure), a plurality of third pads (202, an encircled grouping, See annotated figure) on the second bottom surface and connected to the plurality of first pads, and a plurality of fourth pads (202, an encircled grouping, See annotated figure) on the second bottom surface and connected to the plurality of second pads;
and a fillet layer (Fig. 26: 210) between the first and second semiconductor chips (vertically between) and surrounding the plurality of first pads, the plurality of second pads, the plurality of third pads, and the plurality of fourth pads (horizontally surrounding), wherein a distance between bottom surfaces of the plurality of first pads and the second bottom surface is less than a distance between bottom surfaces of the plurality of second pads and the second bottom surface (“less than” because of the cited heights mapped to limitation “a second height greater than the first height” cited earlier in the claim).
Huang fails to teach “each of the plurality of second pads having a second width less than the first width”.
Lin discloses a plurality of first pads (Fig. 1I: MP1) on the first top surface, each of the plurality of first pads having a first width (W1, See Fig. 1G for measurement markings) and a first height (See dashed reference line in annotated figure); a plurality of second pads (MP2) on the first top surface further outward from a center of the first semiconductor chip (AR1) than the plurality of first pads (See Fig. 1G showing 118B/MP2 “further outward”), each of the plurality of second pads having a second width (W2, See Fig. 1G for measurement markings) less than the first width ([0033]: “width W1…is greater than…width W2”) and a second height (See dashed reference line in annotated figure) greater than the first height (greater height is shown).
Modifying the first and second widths of Huang by including the width configuration of Lin would arrive at the claimed widths. Lin provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the width configuration in that it would improve package reliability by improving connections to the pads ([0046]: “the warpage problem may be compensated and the cold joint problem may be prevented”). A person of ordinary skill in the art before the effective filing date would have predictable results incorporating the width configuration because in Huang and Lin each teach pad dimensions are designed according to chip warpage (Huang: [0011]: “variable heights to account for any warpage”; Lin: [0046]: “By designing the heights and widths”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed width configuration because it would improve package reliability.
Regarding claim 12, Huang in view of Lin discloses the semiconductor package of claim 11, wherein the second top surface is flat (Huang: [0079]: “the encapsulant 212 is thinned such that top surfaces of the encapsulant 212, the integrated circuit devices 50, and die packages 100 are level” describes a grinding operation that would produce the claimed “flat” surface.).
Regarding claim 13, Huang in view of Lin discloses the semiconductor package of claim 11 (Huang: Fig. 14), wherein a distance between the second bottom surface and the plurality of first pads (vertical distance, See annotated figure) is the same as a distance between the second bottom surface and the plurality of second pads (vertical distance. “same” appears to be illustrated and there is no disclosure to the contrary).
Regarding claim 14, Huang in view of Lin discloses the semiconductor package of claim 11 (Huang: Fig. 14), wherein the second bottom surface is convex (a convex shape is shown).
Regarding claim 15, Huang in view of Lin discloses the semiconductor package of claim 11 (Huang: Fig. 14), further comprising: a plurality of first bumps (some of 206A) between (vertically between) the plurality of first pads and the plurality of third pads, and wherein the plurality of first bumps are surrounded (horizontally surrounded. See Fig. 26) by the fillet layer; and a plurality of second bumps (others of 206A) between (vertically between) the plurality of second pads and the plurality of fourth pads, and wherein the plurality of second bumps are surrounded (horizontally surrounded. See Fig. 26) by the fillet layer.
Regarding claim 18, Huang in view of Lin discloses the semiconductor package of claim 11 (Huang: Fig. 26), wherein the first semiconductor chip comprises a substrate (172) and a plurality of through electrodes (174) extending through the substrate (vertically through) and connected to the plurality of first pads and the plurality of second pads (electrically connected).
Regarding independent claim 20, Huang discloses a semiconductor package (Fig. 14) comprising:
a first semiconductor chip (170) comprising a first top surface (See annotated figure) and an opposite first bottom surface (See annotated figure);
a second semiconductor chip (100) comprising a second top surface (See annotated figure) and an opposite second bottom surface (See annotated figure); a fillet layer (Fig. 26: 210) in a gap between the first and second semiconductor chips (vertically between);
and a molding member (212) covering (directly partially covering) the first semiconductor chip, the second semiconductor chip, and the fillet layer,
wherein the first semiconductor chip comprises a plurality of first pads (204A, an encircled grouping, See annotated figure. Note: the examiner is interpreting the structures of Huang as “pads”, consistent with the “pads” in Fig. 3 of Applicant’s disclosure) on the first top surface, each of the plurality of first pads having a first width (horizontal width. See annotated figure for direction designation) and a first height (vertical height),
a plurality of second pads (204A, an encircled grouping, See annotated figure) on the first top surface, each of the plurality of second pads having a second width (horizontal width) […] and a second height (vertical height) greater than the first height (shown by exaggerated heights in the figure; [0063]: “varying heights to account for the warpage and/or curve of the die”),
a plurality of first bumps (some of 206A) on the plurality of first pads, a plurality of second bumps (others of 206A) on the plurality of second pads, and a plurality of through electrodes (Fig. 26: 172) extending through (vertically through) a substrate (174) of the first semiconductor chip and connected to the plurality of first pads and the plurality of second pads (electrically connected),
wherein the second semiconductor chip comprises a plurality of third pads (202, an encircled grouping, See annotated figure) on the second bottom surface and connected to the plurality of first bumps, and a plurality of fourth pads (202, an encircled grouping, See annotated figure) on the second bottom surface and connected to the plurality of second bumps, and wherein the second bottom surface is convex (a convex shape is shown).
Huang fails to teach “each of the plurality of second pads having a second width less than the first width”.
Lin discloses a plurality of first pads (Fig. 1I: MP1) on the first top surface, each of the plurality of first pads having a first width (W1, See Fig. 1G for measurement markings) and a first height (See dashed reference line in annotated figure), a plurality of second pads (MP2) on the first top surface, each of the plurality of second pads having a second width (W2, See Fig. 1G for measurement markings) less than the first width ([0033]: “width W1…is greater than…width W2”) and a second height (See dashed reference line in annotated figure) greater than the first height (greater height is shown).
Modifying the first and second widths of Huang by including the width configuration of Lin would arrive at the claimed widths. Lin provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the width configuration in that it would improve package reliability by improving connections to the pads ([0046]: “the warpage problem may be compensated and the cold joint problem may be prevented”). A person of ordinary skill in the art before the effective filing date would have predictable results incorporating the width configuration because in Huang and Lin each teach pad dimensions are designed according to chip warpage (Huang: [0011]: “variable heights to account for any warpage”; Lin: [0046]: “By designing the heights and widths”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed width configuration because it would improve package reliability.
Claims 1, 10-11, and 19 are rejected under 35 U.S.C. 103 as being obvious over Park (KR 20240011513 A) in view of Lin.
The applied reference has a common Applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding independent claim 1, Park discloses a semiconductor package (Fig. 3b) comprising:
a first semiconductor chip (200) comprising a first top surface (See annotated figure) and an opposite first bottom surface (See annotated figure);
a plurality of first pads (some of 206) on the first top surface, each of the plurality of first pads having a first width (X width) and a first height (Z height);
a plurality of second pads (others of 206) on the first top surface further outward (“outward” in the X direction) from a center of the first semiconductor chip (See annotated figure for center region demarcation) than the plurality of first pads, each of the plurality of second pads having a second width (X width) […] and a second height (Z height) […];
and a second semiconductor chip (210) comprising a second bottom surface (See annotated figure) which faces the first top surface, and an opposite second top surface (See annotated figure),
a plurality of third pads (some of 217) on the second bottom surface and connected to the plurality of first pads (connected by 215), and
a plurality of fourth pads (others of 217) on the second bottom surface and connected to the plurality of second pads (connected by215), wherein the second bottom surface is convex (a convex shape is shown).
Illustrated below is a marked and annotated figure of Fig. 3b of Park.
PNG
media_image4.png
377
662
media_image4.png
Greyscale
Park fails to teach “each of the plurality of second pads having a second width less than the first width and a second height greater than the first height”.
Lin discloses a plurality of first pads (Fig. 1I: MP1) on the first top surface, each of the plurality of first pads having a first width (W1, See Fig. 1G for measurement markings) and a first height (See dashed reference line in annotated figure); a plurality of second pads (MP2) on the first top surface further outward from a center of the first semiconductor chip (AR1) than the plurality of first pads (See Fig. 1G showing 118B/MP2 “further outward”), each of the plurality of second pads having a second width (W2, See Fig. 1G for measurement markings) less than the first width ([0033]: “width W1…is greater than…width W2”) and a second height (See dashed reference line in annotated figure) greater than the first height (greater height is shown).
Modifying the first and second widths and heights of Park by including the width and height configuration of Lin would arrive at the claimed width and height configuration. Lin provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the width configuration in that it would improve package reliability by improving connections to the pads ([0046]: “the warpage problem may be compensated and the cold joint problem may be prevented”). A person of ordinary skill in the art before the effective filing date would have predictable results incorporating the width configuration because Park and Lin each teach pad dimensions are designed according to chip warpage (Park: pg. 7 of translation: “a smile-shaped warpage may occur”; Lin: [0046]: “By designing the heights and widths”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed width and height configuration because it would improve package reliability.
Regarding claim 10, Park in view of Lin discloses the semiconductor package of claim 1 (Park: Fig. 3b), further comprising: a third semiconductor chip (220) on the second semiconductor chip (on in the Z direction) and comprising a third bottom surface (See annotated figure) which faces the second top surface, and an opposite third top surface (See annotated figure), wherein the second semiconductor chip further comprises
a plurality of fifth pads (some of 216) on the second top surface, wherein each of the plurality of fifth pads has a third width (X width) and a third height (Z height), and
a plurality of sixth pads (others of 216) on the second top surface further outward (“outward” in the X direction) from a center of the second semiconductor chip (See annotated figure for center region demarcation) than the plurality of fifth pads, and
wherein each of the plurality of sixth pads have a fourth width (X width) less than the third width (Note: the width configuration of Lin is reasonably applied here in the same way because the scenario is also the same, i.e., bonding warped chips) and a fourth height (Z height) greater than the third height (Note: the height configuration of Lin is reasonably applied here in the same way because the scenario is also the same, i.e., bonding warped chips), and wherein the third bottom surface is convex (a convex shape is shown).
Regarding independent claim 11, Park discloses a semiconductor package (Fig. 3b) comprising:
a first semiconductor chip (200) comprising a first top surface (See annotated figure) and an opposite first bottom surface (See annotated figure);
a plurality of first pads (some of 206) on the first top surface, each of the plurality of first pads having a first width (X width) and a first height (Z height);
a plurality of second pads (others of 206) on the first top surface further outward (“outward” in the X direction) from a center of the first semiconductor chip (See annotated figure for center region demarcation) than the plurality of first pads, each of the plurality of second pads having a second width (X width) […] and a second height (Z height) […];
a second semiconductor chip (210) comprising a second bottom surface (See annotated figure) which faces the first top surface, an opposite second top surface (See annotated figure),
a plurality of third pads (some of 217) on the second bottom surface and connected to the plurality of first pads (connected by 215), and
a plurality of fourth pads (others of 217) on the second bottom surface and connected to the plurality of second pads (connected by 215);
and a fillet layer (a portion of 400) between the first and second semiconductor chips (between in the Z direction) and surrounding the plurality of first pads, the plurality of second pads, the plurality of third pads, and the plurality of fourth pads (surrounding in the X direction), […].
Park fails to teach “each of the plurality of second pads having a second width less than the first width and a second height greater than the first height […] wherein a distance between bottom surfaces of the plurality of first pads and the second bottom surface is less than a distance between bottom surfaces of the plurality of second pads and the second bottom surface”.
Lin discloses a plurality of first pads (Fig. 1I: MP1) on the first top surface, each of the plurality of first pads having a first width (W1, See Fig. 1G for measurement markings) and a first height (See dashed reference line in annotated figure);
a plurality of second pads (MP2) on the first top surface further outward from a center of the first semiconductor chip (AR1) than the plurality of first pads (See Fig. 1G showing 118B/MP2 “further outward”),
each of the plurality of second pads having a second width (W2, See Fig. 1G for measurement markings) less than the first width ([0033]: “width W1…is greater than…width W2”) and a second height (See dashed reference line in annotated figure) greater than the first height (greater height is shown), […]
wherein a distance between bottom surfaces of the plurality of first pads and the second bottom surface (surface of 300) is less than a distance between bottom surfaces of the plurality of second pads and the second bottom surface.
Modifying the first and second widths and heights of Park, and the resultant distances produced from them by including the width configuration of Lin would arrive at the claimed width, height, and distance configuration. Lin provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the configuration in that it would improve package reliability by improving connections to the pads ([0046]: “the warpage problem may be compensated and the cold joint problem may be prevented”). A person of ordinary skill in the art before the effective filing date would have predictable results incorporating the width configuration because Park and Lin each teach pad dimensions are designed according to chip warpage Park and Lin each teach pad dimensions are designed according to chip warpage (Park: pg. 7 of translation: “a smile-shaped warpage may occur”; Lin: [0046]: “By designing the heights and widths”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed width configuration because it would improve package reliability.
Regarding claim 19, Park in view of Lin discloses the semiconductor package of claim 11 (Park, Fig. 3b), wherein the first and second semiconductor chips comprise high-bandwidth memories (HBMs) (pg. 12 of translation: “an HBM”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM H ANDERSON/ Examiner, Art Unit 2817