DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on January 15, 2026. Claims 1, 14 and 24 have been amended. No new claims have been added. Claims 1-10 and 20 have been canceled. Currently, claims 11-19 and 21-31 are pending.
Response to Arguments
Applicant’s amendment to claim 24, “amorphous polycrystalline silicon (a-Si)” does not overcome the claim objection set forth in the previous Office Action. Amorphous silicon (a-Si) has a non-crystalline atomic structure while polycrystalline silicon (poly-Si) consists of small, ordered crystalline grains. Therefore, a material cannot be both amorphous (no crystals) and polycrystalline (many crystals) simultaneously.
Applicant’s arguments with respect to Zhu failing to teach the newly added limitation to claim 11, “wherein removal of a second sidewall between the first dielectric layer and the second dielectric layer exposes surfaces of the first channel layers and surfaces of the second channel layers;” are not found persuasive. The amendment is in indefinite as the Applicant is trying to describe the device in a product by process limitation. The claim fails to positively recite the final structure of the device rendering it indefinite. A second sidewall is not required as part of the device structure.
Claim 14 lacks a proper antecedent basis because it refers to the “second sidewall” without positively reciting its existence in the claim structure. The removed second sidewall is not a necessary structural component however the resulting gap described by the amendment is taught by Zhu, suggesting the amendment does not distinguish the invention from prior art.
Claim Objections
Claim 24 is objected to because of the following informalities: “amorphous polycrystalline silicon (a-Si)” is objected since amorphous silicon (a-Si) has a non-crystalline atomic structure while polycrystalline silicon (poly-Si) consists of small, ordered crystalline grains. Therefore, a material cannot be both amorphous (no crystals) and polycrystalline (many crystals) simultaneously. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-19 and 21-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 11, the claim recites, “wherein removal of a second sidewall between the first dielectric layer and the second dielectric layer exposes surfaces of the first channel layers and surfaces of the second channel layers” which is indefinite due to improper product by process phrasing and a lack of positive structural recitations. The applicant is trying to define the device by a process limitation rather than the resulting structure itself. The claim fails to positively recite the final structure of the device rendering it indefinite. A second sidewall is not required as part of the device structure. It is also not clear if the surfaces of the first and second channel layers are exposed or not in the final product.
Claims 12-19 and 21-31 depend upon claim 11 and do not rectify the problem therefore, they are also rejected.
Regarding claim 14, the claim recites, “a gap formed by removing the second sidewall between the first dielectric layer and the second dielectric layer”, which is indefinite as it lacks proper antecedent basis because it refers to the “second sidewall” without positively reciting its existence in the claim structure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-12, 18 and 25-27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chan et al. (US 2022/0068725 A1; hereafter Chan).
Regarding claim 11, Chan teaches a semiconductor device (see e.g., Figures 1-12) comprising:
a substrate (see e.g., substrate 100, Para [0084], Figures 2-12);
a first sidewall disposed perpendicularly to the substrate (see e.g., the insulating wall 108 disposed perpendicular to the substrate 100, Para [0085], Figures 2-12) and comprising:
a first side (see e.g., the insulating wall 108 has a first side on which layer stack 102 within device region 118 is disposed, Figure 2-12);
a second side; and (see e.g., the insulating wall 108 has a second side on which layer stack 104 within device region 120 is disposed, Figure 2-12)
a third side (see e.g., the insulating wall 108 features a third side along the X-direction, forming a three-dimensional structure. Layer stacks 102 and 104 within device regions 118 and 120 respectively extend along this third direction, Figure 2-12);
a plurality of first channel layers sequentially spaced apart on the first side along a first direction perpendicular to the substrate (see e.g., channel layers 114, which are part of the layer stack 102, within the device region 118 are sequentially spaced apart along a direction perpendicular to the substrate, Para [0087], Figure 2-12), wherein each of the first channel layers is configured to extend along the third side (see e.g., channel layers 114, which are part of the layer stack 102, within the device region 118 extend along the third direction, Figure 2-12), and wherein the first channel layers comprise:
first ends (see e.g., channel layers 114, which are part of the layer stack 102, within the device region 118 have first ends. The source/drain regions 136/138 within device region 118 are disposed at the first ends, Para [0106], Figures 2-12);
a first surface located away from the first sidewall and comprising:
a second end; and a third end (see e.g., Although Figures 11-12 provide a 2D cross-sectional view, they represent a 3D FET structure. Within this 3D structure the channel layers 114 of the FET structure 150 have a first surface with second and third ends. The two gate spacers 134, which are situated on opposing sides of the gate stack 146, are disposed at the second and third ends, Para [0103]);
a second surface located adjacent to the first surface and parallel with the substrate and comprising:
a fourth end; and a fifth end (see e.g., Although Figures 11-12 provide a 2D cross-sectional view, they represent a 3D FET structure. Within this 3D structure the channel layers 114 of the FET structure 150 have a second surface adjacent to the first surface and parallel with the substrate 100 with fourth and fifth ends. The inner spacers 137, which are located at positions from where the gate spacers 134 are absent, are disposed at the fourth end and the fifth end, Para [0107]);
a plurality of second channel layers sequentially spaced apart on the second side along the first direction (see e.g., channel layers 114, which are part of the layer stack 104, within the device region 120 are sequentially spaced apart along a direction perpendicular to the substrate, Para [0087], Figure 2-12), wherein each of the second channel layers is configured to extend along the third side (see e.g., channel layers 114, which are part of the layer stack 104, within the device region 120 extend along the third direction, Figure 2-12), and wherein the first channel layers comprise:
sixth ends (see e.g., channel layers 114, which are part of the layer stack 104, within the device region 120 have sixth ends. The source/drain regions 136/138 within the device region 120 are disposed at the sixth ends, Para [0106], Figures 2-12);
a third surface located away from the first sidewall and comprising:
a seventh end; and
an eighth end (see e.g., Although Figures 11-12 provide a 2D cross-sectional view, they represent a 3D FET structure. Within this 3D structure the channel layers 114 of the FET structure 152 have a third surface with seventh and eighth ends. The two gate spacers 134, which are situated on opposing sides of the gate stack 146, are disposed at the seventh and eighth ends, Para [0103]);
a fourth surface located adjacent to the third surface and parallel with the substrate and comprising:
a ninth end; and
a tenth end (see e.g., Although Figures 11-12 provide a 2D cross-sectional view, they represent a 3D FET structure. Within this 3D structure the channel layers 114 of the FET structure 152 have a fourth surface adjacent to the third surface and parallel with the substrate 100 with ninth and tenth ends. The inner spacers 137, which are located at positions from where the gate spacers 134 are absent, are disposed at the ninth end and the tenth end, Para [0107]);
a first doped structure disposed at the first ends and comprising a first doping type (see e.g., Although Figure 9 provides a 2D cross-sectional view, it represents a 3D FET structure. Within this 3D structure the doped source/drain regions 136/138 within the device region 118 are disposed at the first ends);
a second doped structure disposed at the sixth ends and comprising a second doping type (see e.g., Although Figure 9 provides a 2D cross-sectional view, it represents a 3D FET structure. Within this 3D structure the doped source/drain regions 136/138 within the device region 120 are disposed at the sixth ends),
wherein the first doping type is opposite to the second doping type (see e.g., the source and drain regions 136, 138 in the first device region 118 may be doped with a p-type dopant (to form a p-type nanosheet transistor structure). The source and drain regions 136, 138 in the second device region 120 may be doped with an n-type dopant (to form an n-type nanosheet transistor structure, Para [0106], Figure 9).
a first dielectric layer configured to cover the second end and the seventh end (see e.g., within the 3D FET structure, one of the two gate spacers 134 covers the second and the seventh ends, Figure 9);
a second dielectric layer configured to cover the third end and the eighth end (see e.g., within the 3D FET structure, another of the two gate spacers 134 covers the third and the eight ends, Figure 9);
a third dielectric layer disposed at the fourth end and the fifth end (see e.g., within the 3D FET structure inner spacers 137, within the device region 118, are disposed at the fourth and the fifth ends, Figure 9);
a fourth dielectric layer disposed at the ninth end and the tenth end (see e.g., within the 3D FET structure inner spacers 137, within the device region 120, are disposed at the ninth and the tenth ends, Figure 9);
wherein removal of a second sidewall between the first dielectric layer and the second dielectric layer exposes surfaces of the first channel layers and surfaces of the second channel layers;
The claim limitation “wherein removal of a second sidewall between the first dielectric layer and the second dielectric layer exposes surfaces of the first channel layers and surfaces of the second channel layers” is a product by process limitation. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) See MPEP 2113.
In the instant case, while Chan may not teach the process of removal of a second sidewall between the first dielectric layer and the second dielectric layer exposes surfaces of the first channel layers and surfaces of the second channel layers, no patentable weight is afforded to the removal of second sidewall between the first dielectric layer and the second dielectric layer exposes surfaces of the first channel layers and surfaces of the second channel layers. Therefore, it is maintained that Chan recites the same product.
a first gate insulation layer and a first gate conductive layer sequentially disposed on the exposed surfaces of the first channel layers; and (see e.g., gate stack of the FET structure 150 includes a composite structure comprising a gate dielectric layer (such as a high-k dielectric e.g. HfO.sub.2, HfSiO, LaO, AlO or ZrO) on the channel layers 114 and one or more effective work function metal (WFM) layers on the gate dielectric layer, Paras [0014] – [0015], Figure 12; Examiner’s interpretation: exposed surfaces are unclear)
a second gate insulation layer and a second gate conductive layer sequentially disposed on the exposed surfaces of the second channel layers (see e.g., gate stack of the FET structure 152 includes a composite structure comprising a gate dielectric layer (such as a high-k dielectric e.g. HfO.sub.2, HfSiO, LaO, AlO or ZrO) on the channel layers 114 and one or more effective work function metal (WFM) layers on the gate dielectric layer, Paras [0014] – [0015], Figure 12; Examiner’s interpretation: exposed surfaces are unclear).
Regarding claim 12, Chan, as referred in claim 11, further teaches
further comprising a fifth dielectric layer disposed on the substrate (see e.g., bottom insulating layer material 124 disposed on the substrate, Paras [0095] – [0099], Figures 7-12), wherein the first channel layers, the second channel layers, the first doped structure, and the second doped structure are located on the fifth dielectric layer (see e.g., the channel layers 114 and the source/drain regions 136/138 within the device regions 118 and 120 are located on the bottom insulating material 124, Figures 7 and 9-12).
Regarding claim 18, Chan, as referred in claim 11, further teaches
wherein the first gate conductive layer and the second gate conductive layer comprise a metal material (see e.g., the WFM layers comprise a metal material in both the FET structures 150 and 152. These are either n-type WFM such as TiAl or TiAlC or a p-type WFM such as TiN or TaN).
Regarding claim 25, Chan, as referred in claim 11, further teaches
wherein the first doped structure comprises N-type doping, and wherein the second doped structure comprises P-type doping (see e.g., source/drain regions 136/138 in the device region 120 maybe doped with n-type dopant and the in the device region 118 maybe doped with p-type dopants, Para [0106], Figure 9).
Regarding claim 26, Chan, as referred in claim 11, further teaches
further comprising an electrode structure formed on the first gate conductive layer and the second gate conductive layer (see e.g., a gate fill metal layer is deposited over the WFM layers to form the gate stacks 146 and 148, Para [0118], Figure 12).
Regarding claim 27, Chan, as referred in claim 26, further teaches
wherein the electrode structure configured to facilitate application of a voltage to the first gate conductive layer and the second gate conductive layer (see e.g., contacts are formed for the gate stacks 146/148 to incorporate the transistor structure into a functioning circuit, Para [0119]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13, 19 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0068725 A1; hereafter Chan).
Regarding claim 13, Chan, as referred in claim 11, does not explicitly teach
“wherein first materials of the first gate insulation layer and the second gate insulation layer are the same, and wherein second materials of the first gate conductive layer and the second gate conductive layer are the same”.
Chan discloses a process that deposits a gate dielectric layer into both the first and second gate trenches (142, 144) of the respective FET structures (150, 152). Likewise, Chan teaches the deposition of work function metal (WFM) layer of either p-type or n-type material within these gate trenches.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to use the same material for the gate dielectric layer and WFM layers for both the FETs. Using same materials for the gate dielectric in both devices minimizes cost and production time. Using the same WFM in both devices ensures the channels have the same intrinsic threshold voltage.
Regarding claim 19, Chan, as referred in claim 11, does not explicitly teach
“wherein the first gate conductive layer and the second gate conductive layer are the same”.
Chan discloses a process that deposits a work function metal (WFM) layer of either p-type or n-type material into both the first and second gate trenches (142, 144) of the respective FET structures (150, 152).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to use the same material for the WFM layers for both the FETs. Using the same WFM in both devices ensures the channels have the same intrinsic threshold voltage.
Regarding claim 22, Chan, as referred in claim 11, further teaches
wherein gate insulation layer comprise hafnium dioxide (HfO2) (see e.g., each gate structure 142 and 144 in the respective FET structures 150 and 152 have gate dielectric layer such as HfO.sub.2).
Chan does not explicitly teach
“wherein the first gate insulation layer and the second gate insulation layer comprise hafnium dioxide (HfO2)”.
Chan discloses a process that deposits a gate dielectric layer into both the first and second gate trenches (142, 144) of the respective FET structures (150, 152).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to use the same material for the gate dielectric layer for both the FETs. Using same materials for the gate dielectric in both devices minimizes cost and production time.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0068725 A1; hereafter Chan) in view of Zhu et al. (US 2023/0187497 A1; hereafter Zhu).
Regarding claim 14, Chan, as referred in claim 11, does not explicitly teach
“further comprising:
a gap formed by removing the second sidewall between the first dielectric layer and the second dielectric layer;
a fifth surface in contact with the gap and located in the first channel layers; and a sixth surface in contact with the gap and located in the second channel layers,
wherein the first gate insulation layer and the first gate conductive layer are sequentially disposed on the fifth surface,
wherein the second gate insulation layer and the second gate conductive layer are sequentially disposed on the sixth surface,
wherein first materials of the first gate insulation layer and the second gate insulation layer are the same, and
wherein second materials of the first gate conductive layer and the second gate conductive layer are the same”.
In a similar field of endeavor Zhu teaches
further comprising:
a gap formed by removing the second sidewall between the first dielectric layer and the second dielectric layer (see e.g., in the embodiments shown in Figures 22(a) and 23 there is gap instead of a dielectric structure between the channels or between the gate spacers 1063, Paras [0084]);
Chan teaches a gap which is formed in a manner different from removing the second sidewall between the first dielectric layer and the second dielectric layer. The claim limitation “formed by removing the second sidewall between the first dielectric layer and the second dielectric layer” is a product by process limitation. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) See MPEP 2113.
In the instant case, while Chan may not teach “formed by removing the second sidewall between the first dielectric layer and the second dielectric layer”, no patentable weight is afforded to “formed by removing the second sidewall between the first dielectric layer and the second dielectric layer”. Therefore, it is maintained that Chan recites the same product (that is, the gap), regardless if achieved by a separate process.
a fifth surface in contact with the gap and located in the first channel layers; and a sixth surface in contact with the gap and located in the second channel layers (see e.g., a fifth surface of the first channels and a sixth surface of the second channel layers are in contact with the gap, Figures 22a and 23),
wherein the first gate insulation layer and the first gate conductive layer are sequentially disposed on the fifth surface (see e.g., a gate dielectric layer 1071 and a work function adjustment metal are sequentially disposed on the fifth surface, Para [0091], Figures 22a and 23),
wherein the second gate insulation layer and the second gate conductive layer are sequentially disposed on the sixth surface (see e.g., a gate dielectric layer 1071 and a work function adjustment metal are sequentially disposed on the sixth surface, Para [0091], Figures 22a and 23),
wherein first materials of the first gate insulation layer and the second gate insulation layer are the same, and
wherein second materials of the first gate conductive layer and the second gate conductive layer are the same (see e.g., As shown in Figure 22a gate dielectric and work function adjustment metal are same for both the first channels and second channels).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Zhu’s teachings of further comprising: a gap formed by removing a second sidewall between the first dielectric layer and the second dielectric layer; a fifth surface in contact with the gap and located in the first channel layers; and a sixth surface in contact with the gap and located in the second channel layers, wherein the first gate insulation layer and the first gate conductive layer are sequentially disposed on the fifth surface, wherein the second gate insulation layer and the second gate conductive layer are sequentially disposed on the sixth surface, wherein first materials of the first gate insulation layer and the second gate insulation layer are the same, and wherein second materials of the first gate conductive layer and the second gate conductive layer are the same in the device of Chang in order to reduce parasitic capacitance.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0068725 A1; hereafter Chan) in view of Zhang et al. (US 2021/0358911 A1; hereafter Zhang).
Regarding claim 15, Chan, as referred in claim 11, does not explicitly teach
“wherein materials of the first channel layers and the second channel layers are different”.
In a similar field of endeavor Zhang teaches
wherein materials of the first channel layers and the second channel layers are different (see e.g., For n-type FETs, the channel nanosheets are typically Si and the sacrificial layers are typically SiGe. For p-type FETs, the channel nanosheets can be SiGe and the sacrificial layers can be Si, Para [0037], Figure 3).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Zhang’s teachings of wherein materials of the first channel layers and the second channel layers are different in the device of Chan in order to provide desirable device characteristics, including the introduction of strain at the interface between SiGe and Si.
Regarding claim 16, Chan, as referred in claim 11 further teaches
wherein the first doped structure comprises P-type doping (see e.g., source/drain regions 136/138 in the first device region 118 maybe doped with p-type dopant, Para [0106], Figure 9), wherein the second doped structure comprises N-type doping (see e.g., source/drain regions 136/138 in the second device region 120 maybe doped with n-type dopant, Para [0106], Figure 9),
Chan does not explicitly teach
“wherein the first channel layers comprise silicon-germanium (Si-Ge), and wherein the second channel layers comprise silicon (Si)”.
In a similar field of endeavor Zhang teaches
wherein the first channel layers comprise silicon-germanium (Si-Ge), and wherein the second channel layers comprise silicon (Si) (see e.g., For n-type FETs, the channel nanosheets are typically Si and the sacrificial layers are typically SiGe. For p-type FETs, the channel nanosheets can be SiGe and the sacrificial layers can be Si, Para [0037], Figure 3).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Zhang’s teachings of wherein the first channel layers comprise silicon-germanium (Si-Ge), and wherein the second channel layers comprise silicon (Si) in the device of Chan in order to provide desirable device characteristics, including the introduction of strain at the interface between SiGe and Si.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0068725 A1; hereafter Chan) in view of Miura et al. (US 2021/0082766 A1; hereafter Miura).
Regarding claim 17, Chan, as referred in claim 11, does not explicitly teach
“wherein the first gate insulation layer and the second gate insulation layer comprise silicon dioxide (Si02)”.
In a similar field of endeavor Miura teaches
wherein the first gate insulation layer and the second gate insulation layer comprise silicon dioxide (Si02) (see e.g., gate insulating film may include a thin silicon dioxide SiO.sub.2 layer formed on the surface of the channel, Para [0068], Figure 1A).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Miura’s teachings of wherein the first gate insulation layer and the second gate insulation layer comprise silicon dioxide (Si02) in the device of Chan since the SiO.sub.2 layer acts as a nucleation layer for the deposition of high-k material also its interface with silicon has low density defects.
Claims 21, 23 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0068725 A1; hereafter Chan) in view of Yang et al. (US 2022/0037535 A1; hereafter Yang).
Regarding claim 21, Chan, as referred in claim 11, does not explicitly teach
“wherein the first gate insulation layer and the second gate insulation layer comprise zirconium dioxide (ZrO2)”.
However, Chan teaches the gate insulation layer comprises ZrO which is an obvious variant of ZrO.sub.2 as taught by Yang.
In a similar field of endeavor Yang teaches wherein the first gate insulation layer and the second gate insulation layer comprise zirconium dioxide (ZrO2) (see e.g., for the NFET region 202N, the stacks 210 on the opposing sides of the spacer 212N have gate dielectric layers 240N which include materials such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric material, or combinations thereof, Para [0035], Figure 19A)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yang’s teachings of wherein the first gate insulation layer and the second gate insulation layer comprise zirconium dioxide (ZrO2) in the device of Chan in order to choose any of the alternative material to arrive at the claimed invention.
Regarding claim 23, Chan, as referred in claim 11, does not explicitly teach
“wherein the first gate insulation layer and the second gate insulation layer comprise aluminum oxide (A1203)”.
However, Chan teaches the gate insulation layer comprises AlO which is an obvious variant of Al.sub.2O.sub.3 as taught by Yang.
In a similar field of endeavor Yang teaches wherein the first gate insulation layer and the second gate insulation layer comprise aluminum oxide (A1203) (see e.g., for the NFET region 202N, the stacks 210 on the opposing sides of the spacer 212N have gate dielectric layers 240N which include materials such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric material, or combinations thereof, Para [0035], Figure 19A)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yang’s teachings of wherein the first gate insulation layer and the second gate insulation layer comprise aluminum oxide (A1203) in the device of Chan in order to choose any of the alternative material to arrive at the claimed invention.
Regarding claim 28, Chan, as referred in claim 26, does not explicitly teach
“wherein a material of the electrode structure comprises aluminum or silver”.
In a similar field of endeavor Yang teaches
wherein a material of the electrode structure comprises aluminum or silver (see e.g., bulk metal 244 may include Al, Para [0037], Figure 19A).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yang’s teachings of wherein a material of the electrode structure comprises aluminum or silver in the device of Chan as these are known materials yielding predictable results.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0068725 A1; hereafter Chan) in view of Lilak et al. (US 2020/0411433 A1; hereafter Lilak).
Regarding claim 24, Chan, as referred in claim 11, does not explicitly teach
“wherein the first gate conductive layer and the second gate conductive layer comprise a heavily doped polycrystalline silicon (a-Si)”.
In a similar field of endeavor Lilak teaches
wherein the first gate conductive layer and the second gate conductive layer comprise a heavily doped polycrystalline silicon (a-Si) (see e.g., Work function metal 274 may have any suitable work function and may be an elemental metal layer, a metal alloy layer, or even a doped semiconductor (e.g., polysilicon) layer, Para [0046], Figure 2).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lilak’s teachings of wherein the first gate conductive layer and the second gate conductive layer comprise a heavily doped polycrystalline silicon in the device of Chan in order to control the threshold voltage of the transistor.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0068725 A1; hereafter Chan) in view of Lilak et al. (US 2021/0296315 A1; hereafter Lilak).
Regarding claim 29, Chan, as referred in claim 26, does not explicitly teach
“further comprising an isolation layer disposed on the electrode structure”.
In a similar field of endeavor Lilak teaches
further comprising an isolation layer disposed on the electrode structure (see e.g., an insulator layer 103 disposed over the gate fill metals 113A and 113B, Para [0037], Figure 1B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Zheng’s teachings of further comprising an isolation layer disposed on the electrode structure in the device of Chan in order to provide isolation from surrounding structures.
Claim 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0068725 A1; hereafter Chan) in view of Lilak et al. (US 2021/0296315 A1; hereafter Lilak) and further in view of Yang (US 2022/0093593 A1).
Regarding claim 30, Chan, as modified by Lilak, teaches the limitations of claim 29 as mentioned above. Chan does not explicitly teach
“wherein an insulation material of the isolation layer comprises an oxide”.
In a similar field of endeavor Yang teaches
wherein an insulation material of the isolation layer comprises an oxide (see e.g., a dielectric layer 54 composed of materials such as silicon oxide and silicon nitride, Para [0035], Figure 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yang’s teachings of wherein an insulation material of the isolation layer comprises an oxide in the device of Chan as these are commonly used materials for forming isolation layers. Combining known prior art elements according to known methods to yield predictable results renders a claimed invention obvious.
Regarding claim 31, Chan, as modified by Lilak, teaches the limitations of claim 29 as mentioned above. Chan does not explicitly teach
“wherein an insulation material of the isolation layer comprises a silicon nitride”.
In a similar field of endeavor Yang teaches
wherein an insulation material of the isolation layer comprises a silicon nitride (see e.g., a dielectric layer 54 composed of materials such as silicon oxide and silicon nitride, Para [0035], Figure 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yang’s teachings of wherein an insulation material of the isolation layer comprises a silicon nitride in the device of Chan as these are commonly used materials for forming isolation layers. Combining known prior art elements according to known methods to yield predictable results renders a claimed invention obvious.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893