Prosecution Insights
Last updated: August 18, 2026
Application No. 18/309,308

SEMICONDUCTOR DEVICES WITH DOUBLE-SIDED FANOUT CHIP PACKAGES

Non-Final OA §103§112
Filed
Apr 28, 2023
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Avago Technologies International Sales Pte. Limited
OA Round
3 (Non-Final)
40%
Grant Probability
Moderate
3-4
OA Rounds
1m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 40% of resolved cases
40%
Career Allowance Rate
154 granted / 384 resolved
-27.9% vs TC avg
Strong +31% interview lift
Without
With
+31.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
52 currently pending
Career history
453
Total Applications
across all art units

Statute-Specific Performance

§103
43.8%
+3.8% vs TC avg
§102
16.1%
-23.9% vs TC avg
§112
35.1%
-4.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 384 resolved cases

Office Action

§103 §112
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/6/2026 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 13 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 13, the limitation “a common ground within a portion of the fourth bottom surface,” does not appear to have support in the originally filed disclosure. Specifically, the common ground is disclosed as being within the “fourth thickness” of the third circuit board, but does not disclose it is within the surface. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s)1-6, 8-9, and 13 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the limitation “a first filling material comprising a third thickness between the first top surface and the second top surface” is unclear as to how it is related to the previously recited “third thickness” of the second circuit and as to what is intended by a “thickness” between the first top surface and the second top surface. Specifically, the “thickness” would appear to be defined between the first top surface and a bottom surface of another element as opposed to the second top surface. Regarding claim 1, the limitation “the first conductor” is unclear because it lacks proper antecedent basis and is therefore unclear as to how it is related to the previously recited elements. Regarding claim 1, the limitation “wherein the second circuit board comprises metal traces for the routing connections and the ground connections of the second circuit, the metal traces being electrically coupled to the first top surface of the first circuit board through the plurality of conductive wires to provide electrical connections between the printed circuit board and the first circuit board,” is unclear as to if all of the metal traces are required to be both for routing/grounding and also coupled to the first circuit board. Regarding claim 1, the limitation “the routing connections” is unclear because it lacks proper antecedent basis and is therefore unclear as to how it is related to the previously recited elements. Regarding claim 1, the limitation “the ground connections” is unclear because it lacks proper antecedent basis and is therefore unclear as to how it is related to the previously recited elements. Regarding claim 1, the limitation “the plurality of conductive wires” is unclear because it lacks proper antecedent basis and is therefore unclear as to how it is related to the previously recited elements. Regarding claim 1, the limitation “the printed circuit board” is unclear because it lacks proper antecedent basis and is therefore unclear as to how it is related to the previously recited elements. Regarding claim 1, the limitation “the second circuit comprises a plurality of conductor pads coupled to a bottom surface of the second circuit board,” is unclear as to how “a bottom surface” is related to the previously recited “third bottom surface” of the second circuit. Regarding claim 1, the limitation “the second circuit further comprises a bottom surface” is unclear as to how “a bottom surface” is related to the previously recited “third bottom surface” of the second circuit” and “the second circuit comprises a plurality of conductor pads coupled to a bottom surface of the second circuit board.” Regarding claim 1, the limitation “printed circuit board” is unclear as to what is required by the claim. Specifically, applicant’s disclosure provides the following context for the proper interpretation of “printed circuit board” “the term ‘circuit board’, including the mentioned ‘main circuit board’ and ‘sub-sized circuit board’, also known as a printed circuit board (PCB), refer a flat, rigid board made of insulating material, typically fiberglass or plastic, that contains a complex network of metallic pathways, or ‘traces,’ that form the electrical circuitry for various electronic devices” (see [0015]). This would seem to indicate that a proper interpretation of “printed circuit board” is a flat, rigid board made of insulating material that contains a complex network of metallic pathways that form the electrical circuitry for various electronic devices, noting that “typically fiberglass or plastic,” are merely examples and cannot be taken as limiting, and also noting that “rigid” is a relative term and since the specification does not provide a standard for ascertaining the requisite degree, any degree of rigidity would be understood to meet the scope of printed circuit board. Applicant argues, however, that element 230 of Lee does not read on “printed circuit board,” because the term “PCB” requires a particular method of making and should be a “self-supporting ‘board’ that provides structure rigidity and support.” Accordingly, applicant’s arguments introduce a lack of clarity as to the proper interpretation of the claimed term. Additionally, if Applicant’s argued meaning of printed circuit board is to be applied, “self-supporting,” “rigidity” and “support” are each relative terms and render the claim indefinite. Regarding claim 8, the limitation “a conductor post” is unclear as to how it is related the “plurality of conductor posts,” recited in claim 1. Regarding claim 8, the limitation “the first top surface of the first circuit” is unclear as to how it is related to the first top surface of the first circuit board recited in claim 1. Regarding claim 9, the limitation “a conductor pad” is unclear as to how it is related the “plurality of conductor pads,” recited in claim 1. Regarding claim 9, the limitation “a second front surface of the second circuit board” is unclear as to how it is related to the second top and second bottom surfaces of the second circuit board, recited in claim 1. Regarding claim 13, the limitation “common ground” is unclear as to how it is related to the “ground connections” recited in claim 1. Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Note that the claims have not been rejected over the prior art because, in light of the 35 U.S.C. 112 rejections supra, there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of the claims; hence, it would not be proper to reject the claims on the basis of prior art. As stated in In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims. Response to Arguments Applicant's arguments filed 5/6/2026 have been fully considered but are moot in view of the new grounds of rejection presented above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Show 2 earlier events
Dec 23, 2025
Interview Requested
Jan 21, 2026
Response Filed
Jan 21, 2026
Applicant Interview (Telephonic)
Jan 21, 2026
Examiner Interview Summary
Feb 23, 2026
Final Rejection mailed — §103, §112
May 06, 2026
Request for Continued Examination
May 09, 2026
Response after Non-Final Action
Jul 10, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701831
LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING APPARATUS COMPRISING THE SAME
5y 7m to grant Granted Aug 04, 2026
Patent 12696605
DISPLAY DEVICE AND MANUFACTURING METHOD THEREFOR
3y 6m to grant Granted Jul 28, 2026
Patent 12690222
INNER SPACER LINER FOR GATE-ALL-AROUND DEVICE
2y 7m to grant Granted Jul 21, 2026
Patent 12684905
LIGHT-EMITTING DEVICE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS
2y 6m to grant Granted Jul 14, 2026
Patent 12672278
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
2y 6m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
40%
Grant Probability
72%
With Interview (+31.4%)
3y 5m (~1m remaining)
Median Time to Grant
High
PTA Risk
Based on 384 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month