DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20180190697 A1) hereinafter “Lee.”
Regarding Claim 16, Figures 1-2 of Lee teach: An image sensor (200) comprising a pixel (UP) that comprises: a photoelectric conversion region (PD1-3) in a semiconductor substrate (combination of 1 and PD1-3); a floating diffusion region (FD1-3) that extends into the semiconductor substrate, wherein the floating diffusion region is spaced apart from the photoelectric conversion region (Figure 2); and a vertical transfer gate (TG) that partially surrounds the floating diffusion region in plan view (Figure 1).
Regarding Claim 19, Figures 1-2 of Lee teach: a height of the vertical transfer gate (TG) is greater (Figure 2) than a height of the floating diffusion region (FD1-3) with respect to a surface of the semiconductor substrate (bottom vertically of item 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7, 9, 12-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 20120199882 A1) hereinafter “Shin” in view of Ammo et al. (US 20200020728 A1) hereinafter “Ammo.”
Regarding Claim 1, Figure 4 of Shin teaches: An image sensor (Paragraph 0070) comprising at least one pixel (P), wherein the at least one pixel comprises: a photoelectric conversion region (111) in a semiconductor substrate (100) that has a first surface (1) and a second surface (2) that oppose each other; a floating diffusion region (131) spaced apart from the photoelectric conversion region in the semiconductor substrate; and a vertical transfer gate (123) that extends into the semiconductor substrate from the first surface of the semiconductor substrate, wherein a transfer channel (113; Paragraph 0077) is between the photoelectric conversion region and the floating diffusion region, wherein the vertical transfer gate has an annular shape (Figures 6A-6E) along a periphery of the floating diffusion region in plan view
Shin does not teach: the vertical transfer gate has an opening that is in a charge transfer path from the photoelectric conversion region to the floating diffusion region.
Figures 11A-11G of Ammo teach: a vertical nanowire transistor (Figure 8) with a vertical gate electrode (53) formed as an annular shape, wherein the vertical gate electrode has an opening (Figures 11B-11C and 11E-11G)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the vertical transfer gate has an opening because Ammo teaches the shape capable of being utilized as a vertical gate is not limited to fully surrounding the outer circumference of the inner structure (Ammo Paragraph 0078).
Further, it would be obvious to one of ordinary skill in the art to have the opening be in a charge transfer path from the photoelectric conversion region to the floating diffusion region because the floating diffusion region of Shin acts as a detection device and is configured to receive charges from the photoelectric conversion region (Shin Paragraph 0059).
Regarding Claim 4, Figure 6D of Shin teaches: the annular shape of the vertical transfer gate (123) comprises a circular annular shape.
Regarding Claim 5, Figure 6A of Shin teaches: the annular shape of the vertical transfer gate (123) comprises a rectangular annular shape.
Regarding Claim 7, Figure 4 of Shin teaches: the floating diffusion region (131) extends along a portion of a sidewall (Figure 4) of the vertical transfer gate (123), and wherein a bottom surface (bottom vertically of 131) of the floating diffusion region is separated (Figure 4) from a bottom surface (bottom vertically of 123) of the vertical transfer gate.
Regarding Claim 9, Figure 4 of Shin teaches: a microlens (330) on the second surface (2) of the semiconductor substrate (100).
Regarding Claim 12, Figure 4 of Shin teaches: the at least one pixel (P) further comprises a transistor (Paragraph 0102) on the semiconductor substrate (100).
Regarding Claim 13, Figures 3 and 4 of Shin teach: the semiconductor substrate (100) comprises an active region (ACT1) comprising the at least one pixel (P), and a peripheral region (ACT2) on at least one side of the active region, and wherein a pixel circuit (Paragraph 0073) is in the peripheral region and is configured to control the at least one pixel (Paragraph 0073).
Regarding Claim 14, Figure 4 of Shin teaches: the photoelectric conversion region (111) is configured to receive incident light (Figure 4) through the second surface (2) of the semiconductor substrate.
Regarding Claim 15, Figures 1-4 of Shin teach: An image sensor (Paragraph 0047) comprising: a pixel array (10) comprising a plurality of pixels (Paragraph 0056); and a control unit (30) configured to control the pixel array (Paragraph 0049), wherein each of the plurality of pixels comprises: a photoelectric conversion region (111) in a semiconductor substrate (100) that has a first surface (1) and a second surface (2) that oppose each other; a floating diffusion region (131) spaced apart from the photoelectric conversion region in the semiconductor substrate; and a vertical transfer gate (123) that extends into the semiconductor substrate from the first surface of the semiconductor substrate, wherein a transfer channel (113; Paragraph 0077) is between the photoelectric conversion region and the floating diffusion region, and wherein the vertical transfer gate has an annular shape (Figures 6A-6E) along a periphery of the floating diffusion region in plan view
Shin does not teach: the vertical transfer gate has an opening that is in a charge transfer path from the photoelectric conversion region to the floating diffusion region.
Figures 11A-11G of Ammo teach: a vertical nanowire transistor (Figure 8) with a vertical gate electrode (53) formed as an annular shape, wherein the vertical gate electrode has an opening (Figures 11B-11C and 11E-11G)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the vertical transfer gate has an opening because Ammo teaches the shape capable of being utilized as a vertical gate is not limited to fully surrounding the outer circumference of the inner structure (Ammo Paragraph 0078).
Further, it would be obvious to one of ordinary skill in the art to have the opening be in a charge transfer path from the photoelectric conversion region to the floating diffusion region because the floating diffusion region of Shin acts as a detection device and is configured to receive charges from the photoelectric conversion region (Shin Paragraph 0059).
Regarding Claim 16, Figure 4 of Shin teaches: An image sensor (Paragraph 0070) comprising a pixel (P) that comprises: a photoelectric conversion region (111) in a semiconductor substrate (100); a floating diffusion region (131) that extends into the semiconductor substrate, wherein the floating diffusion region is spaced apart from the photoelectric conversion region (Figure 4); and a vertical transfer gate (123) that surrounds the floating diffusion region in plan view (Figure 3).
Shin does not teach: the vertical transfer gate partially surrounds the floating diffusion region in a plan view
Figures 11A-11G of Ammo teach: a vertical nanowire transistor (Figure 8) with a vertical gate electrode (53) formed as an annular shape, wherein the vertical gate electrode has an opening (Figures 11B-11C and 11E-11G)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the vertical transfer gate partially surround the floating diffusion region in a plan view because Ammo teaches the shape capable of being utilized as a vertical gate is not limited to fully surrounding the outer circumference of the inner structure (Ammo Paragraph 0078).
Regarding Claim 17, Figure 4 of Shin teaches: the floating diffusion region (131) extends into the semiconductor substrate (100) from a top surface (1) of the semiconductor substrate, the image sensor further comprising MOS transistors (Paragraph 0102)
Shin does not teach: a semiconductor pattern on the top surface of the semiconductor substrate; and a gate electrode that surrounds the semiconductor pattern in the plan view, wherein the gate electrode comprises a gate-all-around transistor.
Figure 3 of Ammo teaches: an imaging apparatus (Paragraph 0045) with a plurality of vertical nanowire transistors (TRG, RST, AMP, SEL) comprising a semiconductor pillar (Paragraph 0047) and a gate (G) is formed to surround the semiconductor pillar, as a gate-all-around transistor.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a semiconductor pattern on the top surface of the semiconductor substrate; and a gate electrode that surrounds the semiconductor pattern in the plan view, wherein the gate electrode comprises a gate-all-around transistor because Ammo teaches using vertical nanowire transistors in imaging devices compacts the transistors, allowing an area ratio of the photodiode to improve, improving the number of saturated electrons and light sensitivity (Ammo Paragraph 0055).
Regarding Claim 20, the combination of Shin and Ammo teaches all of the limitations of the claimed invention as stated above.
Shin does not teach: the vertical transfer gate has an opening that is in a charge transfer path from the photoelectric conversion region to the floating diffusion region.
Figures 11A-11G of Ammo teach: a vertical nanowire transistor (Figure 8) with a vertical gate electrode (53) formed as an annular shape, wherein the vertical gate electrode has an opening (Figures 11B-11C and 11E-11G)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the vertical transfer gate has an opening because Ammo teaches the shape capable of being utilized as a vertical gate is not limited to fully surrounding the outer circumference of the inner structure (Ammo Paragraph 0078).
Further, it would be obvious to one of ordinary skill in the art to have the opening be in a charge transfer path from the photoelectric conversion region to the floating diffusion region because the floating diffusion region of Shin acts as a detection device and is configured to receive charges from the photoelectric conversion region (Shin Paragraph 0059).
Claims 6, 8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 20120199882 A1) hereinafter “Shin” in view of Ammo et al. (US 20200020728 A1) hereinafter “Ammo” and Ito et al. (US 20220353449 A1) hereinafter “Ito.”
Regarding Claim 6, the combination of Shin and Ammo teach all of the limitations of the claimed invention as stated above.
Shin does not explicitly teach: a separation layer that extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate adjacent the at least one pixel.
Figure 7 of Ito teaches: an image sensor (1) comprising a plurality of pixels (12) and a separation layer (43) that extends from a first surface (top vertically of 11) of a semiconductor substrate (11) to a second surface (bottom vertically of 11) of a semiconductor substrate adjacent the pixels (Paragraph 0222)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a separation layer that extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate adjacent the at least one pixel because Ito teaches a separation layer electrically separates adjacent sensor pixels from each other (Ito Paragraph 0222).
Regarding Claim 8, the combination of Shin and Ammo teach all of the limitations of the claimed invention as stated above.
Shin does not teach: the separation layer is around at least a portion of a periphery of the at least one pixel in the plan view.
Figure 8 of Ito teaches: the separation layer (43) is around a periphery of the pixels (12) in plan view (Figure 8)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the separation layer is around at least a portion of a periphery of the at least one pixel in the plan view because Ito teaches a separation layer electrically separates adjacent sensor pixels from each other (Ito Paragraph 0222).
Regarding Claim 11, the combination of Shin and Ammo teach all of the limitations of the claimed invention as stated above.
Figure of Shin teaches: the image sensor (Paragraph 0070) comprises a plurality of pixels (Paragraph 0049) including the at least one pixel (P)
Shin does not teach: the floating diffusion region is shared by at least two adjacent pixels of the plurality of pixels.
Figure 55 of Ito teaches: a floating diffusion region (FD) is shared (Paragraph 0500) by at least two adjacent pixels (12)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the floating diffusion region is shared by at least two adjacent pixels of the plurality of pixels because Ito teaches having multiple pixels share a single floating diffusion unit beneficially lowers the amount of wiring lines required by the pixel circuit (Ito Paragraph 0502).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 20120199882 A1) hereinafter “Shin” in view of Ammo et al. (US 20200020728 A1) hereinafter “Ammo” and Ai et al. (US 20210391363 A1) hereinafter “Ai.”
Regarding Claim 10, the combination of Shin and Ammo teach all of the limitations of the claimed invention as stated above.
Figure of Shin teaches: the image sensor (Paragraph 0070) comprises a plurality of pixels (Paragraph 0049) including the at least one pixel (P)
Shin does not teach: the microlens is shared by at least two adjacent pixels of the plurality of pixels.
Figure 1A-1E of Ai teaches: an image sensor (100) comprising a plurality of pixels (105-1, 105-2, 105-3, and 105-4) wherein a microlens (141) is shared by two adjacent pixels (Figures 1D-1E)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the microlens is shared by at least two adjacent pixels of the plurality of pixels because Ai teaches shared microlens tune (i.e., homogenize) the angular selectivity and light sensitivity of the multi-pixel detectors (Ai Paragraph 0017).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 20120199882 A1) hereinafter “Shin” in view of Ammo et al. (US 20200020728 A1) hereinafter “Ammo” and Tsai (US 20220085083 A1) hereinafter “Tsai.”
Regarding Claim 18, the combination of Shin and Ammo teach all of the limitations of the claimed invention as stated above.
The combination of the transistor of Shin and the transistor structure of Ammo will yield a structure such that the gate electrode comprises a main electrode portion, the portion that surrounds the semiconductor pillar.
Shin does not teach: an extension portion having a planar top surface that extends from the main electrode portion.
Figure 3H of Tsai teaches: an imaging device (Paragraph 0051) having a semiconductor post structure (350) with a gate (combination of 340 and 342) surrounding the post structure, wherein the gate comprises a main portion (340) that surrounds the semiconductor post and an extension portion (342) having a planar top surface that extends from the main electrode portion.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have an extension portion having a planar top surface that extends from the main electrode portion because Tsai teaches a gate extension portion acts as a contact landing portion for gate contacts (Tsai Paragraph 0067).
Allowable Subject Matter
Claims 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have the opening overlaps a straight line between the floating diffusion region and a point that represents a maximum potential value, in the photoelectric conversion region along with the other limitations of Claim 1. Claim 3 is also objected to as it depends from and includes all of the limitations of Claim 2.
Conclusion
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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