Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hussain et al (US 2019/0259685, hereinafter Hussain), in view of Tay et al (US 2012/0241928, hereinafter Tay).
With respect to claim 1. Hussain discloses an electronic device (10 of Fig. 1), comprising: a semiconductor die (e.g. 20) having opposite first (e.g. Bottom surface of 20) and second (e.g. Top surface of the 20) sides, a conductive terminal (e.g. 70) on the second side, and an electrical isolation coating layer (e.g. 40, Para 0019) that extends on the first side; a die attach pad (e.g. 100 & 30); an adhesive (e.g. 50) that adheres the first side of the semiconductor die to the die attach pad; a conductive lead (e.g. 90) electrically coupled to the conductive terminal of the semiconductor die; and a package structure (e.g. top portion of 100) that encloses at least a portion of the semiconductor die.
Hussain does not explicitly disclose that is a non-conductive/electrical isolation material.
In analogous art, Tay disclose that in indeed a non-conductive/electrically isolated/insulated material (e.g. Para 0038).
Therefore, it would have been obvious to one of an ordinary skilled in the art to use insulated material as disclosed by Tay to minimize parasitic.
With respect to claim 8. Hussain/Tay discloses the electronic device of claim 1, wherein the electrical isolation coating layer has a high thermal conductivity (i.e. 8006NS having thermal conductivity).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hussain /Tay further in view of Ogata (US 2004/0245652, hereinafter Ogata).
With respect to claim 2. Hussain/Tay discloses the electronic device of claim 1.
Hussain/Tay does not disclose the semiconductor die has a lateral sidewall that extends between the first and second sides and an indent that extends into a portion of the lateral sidewall and to the first side; and the electrical isolation coating layer extends along the indent and on the first side.
In analogous art, Ogata discloses the semiconductor die (e.g. 5a of Fig. 2C) has a lateral sidewall that extends between the first and second sides and an indent (e.g. 5e) that extends into a portion of the lateral sidewall and to the first side; and the electrical isolation coating layer (e.g. 5c) extends along the indent and on the first side.
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Hussain/Tay’s disclosed invention and form indent to avoid electrical shorts (e.g. Para 0020).
With respect to claim 3. Hussain/Tay/Ogata discloses the electronic device of claim 2, wherein the electrical isolation coating layer has a high thermal conductivity (i.e. 8006NS having thermal conductivity).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hussain /Tay/Ogata further in view of 8006NS TDS (Loctite Ablestik 8006NS Datasheet, hereinafter TDS).
With respect to claim 5. Hussain/Tay/Ogata discloses the electronic device of claim 2.
Hussain/Tay/Ogata does not explicitly disclose wherein the electrical isolation coating layer includes at least one of silicon dioxide, parylene, and polyimide.
In an analogous art, TDS discloses the 8006NS to be containing Silica (silicon dioxide).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to use silica to achieve high thermal conductivity and low electrical conductivity.
Claims 6 - 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hussain /Tay/Ogata further in view Veeramma (US 2006/0246642, hereinafter Veeramma).
With respect to claim 6 & 7. Hussain/Tay/Ogata discloses the electronic device of claim 2.
Hussain/Tay/Ogata does not disclose wherein the electrical isolation coating layer has a thickness of approximately 0.1 um or more and approximately 10 um or less.
In an analogous art, Veeramma discloses the electrical isolation coating layer has a thickness of approximately 0.1 um or more and approximately 10 um or less (abstract).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Hussain/Tay/Ogata’s disclosure and form isolation coating layer having such thickness to ensure adequate electrical isolation and stress relief.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hussain /Tay further in view of TDS.
With respect to claim 9. Hussain/Tay/Ogata discloses the electronic device of claim 1.
Hussain/Tay does not explicitly disclose wherein the electrical isolation coating layer includes at least one of silicon dioxide, parylene, and polyimide.
In an analogous art, TDS discloses the 8006NS to be containing Silica (silicon dioxide).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to use silica to achieve high thermal conductivity and low electrical conductivity.
Claims 10 - 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hussain /Tay further in view Veeramma.
With respect to claim 10 & 11. Hussain/Tay/Ogata discloses the electronic device of claim 1.
Hussain/Tay/Ogata does not disclose wherein the electrical isolation coating layer has a thickness of approximately 0.1 um or more and approximately 10 um or less.
In an analogous art, Veeramma discloses the electrical isolation coating layer has a thickness of approximately 0.1 um or more and approximately 10 um or less (abstract).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Hussain/Tay/Ogata’s disclosure and form isolation coating layer having such thickness to ensure adequate electrical isolation and stress relief.
Claim 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja (US 2011/0147919, hereinafter Sutardja).
With respect to claim 12. A system (Fig. 5), comprising: a circuit board (102); and an electronic device (900) having a die attach pad (850), a conductive lead (110), a semiconductor die (104), and a package structure (Fig. 5), wherein: the semiconductor die has opposite first (bottom) and second (top) sides, a conductive terminal (108) on the second side, and an electrical isolation coating layer (514) that extends on the first side; the adhesive adheres the first side of the semiconductor die to the die attach pad (as disclosed); the conductive lead is electrically coupled to the conductive terminal of the semiconductor die (110 is connected to pads on the surface 102) and to a conductive feature of the circuit board; and the package structure encloses at least a portion of the semiconductor die.
Sutardja embodiment of figure 5 does not explicitly disclose the an adhesive.
However, in another embodiment Sutardja discloses the adhesive (Para 004) to attach other elements of the semiconductor devices.
Claim 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja in view of Semiconductor package and method of manufacturing the semiconductor package (KR 2021/0045597, hereinafter ‘597).
With respect to claim 14. Sutardja discloses the system of claim 12.
Sutardja does not disclose wherein the electrical isolation coating layer has a high thermal conductivity and wherein, the electrical isolation coating layer includes at least one of silicon dioxide, parylene, and polyimide.
In an analogous art, ‘597 discloses wherein the electrical isolation coating layer has a high thermal conductivity and wherein, the electrical isolation coating layer includes at least one of silicon dioxide, parylene, and polyimide. (Description attached).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Sutardja’s disclosure and form underfill with silicon oxide to achieve optimum insulation and superior thermal conductivity.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Sutardja in view Veeramma.
With respect to claim 16. Sutardja discloses the electronic device of claim 12.
Sutardja does not disclose wherein the electrical isolation coating layer has a thickness of approximately 0.1 um or more and approximately 10 um or less.
In an analogous art, Veeramma discloses the electrical isolation coating layer has a thickness of approximately 0.1 um or more and approximately 10 um or less (abstract).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Sutardja’s disclosure and form isolation coating layer having such thickness to ensure adequate electrical isolation and stress relief.
Claims 17 - 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ciavatti et al (US 2019/0131406, hereinafter Ciavatti).
With respect to claim 17. A method of fabricating an electronic device, the method comprising: forming trenches in a first side of a wafer (12 of Fig. 7).
Ciavatti does not explicitly disclose the forming an electrical isolation coating layer on the first side and in the trenches; and separating a semiconductor die from the wafer, the semiconductor die having a portion of the first side, an opposite second side, a conductive terminal on the second side, a lateral sidewall that extends between the first and second sides, an indent that extends into a portion of the lateral sidewall and to the portion of the first side, and a portion of the electrical isolation coating layer that extends along the indent and on the portion of the first side.
However, in associated text of another embodiment Ciavatti discloses disclose the forming an electrical isolation coating layer (Para 0012 – dielectric filled into trenches) on the first side and in the trenches; and separating a semiconductor die from the wafer (Para 0027), the semiconductor die having a portion of the first side (bottom side), an opposite second side (top side), a conductive terminal (34) on the second side, a lateral sidewall that extends between the first and second sides, an indent that extends into a portion of the lateral sidewall and to the portion of the first side (Para 0020, indent extending), and a portion of the electrical isolation coating layer that extends along the indent and on the portion of the first side (as shown).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Fig 7 embodiment and form electrical isolation layer as taught in para 0012 to prevent electrical shorts.
With respect to claim 18. Ciavatti discloses the method of claim 17, wherein forming the electrical isolation coating layer includes performing a deposition process that deposits the electrical isolation coating layer on the first side and in the trenches (Para 0012).
With respect to claim 19. Ciavatti discloses the method of claim 17, wherein forming the electrical isolation coating layer includes forming at least one of silicon dioxide, parylene, and polyimide on the first side and in the trenches (Para 0017).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ciavatti in view Veeramma.
With respect to claim 20. Ciavatti discloses the electronic device of claim 17.
Ciavatti does not disclose wherein the electrical isolation coating layer has a thickness of approximately 0.1 um or more and approximately 10 um or less.
In an analogous art, Veeramma discloses the electrical isolation coating layer has a thickness of approximately 0.1 um or more and approximately 10 um or less (abstract).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ciavatti’s disclosure and form isolation coating layer having such thickness to ensure adequate electrical isolation and stress relief.
Claim Objections
Claims 4, 13 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
Prior art of record as applied above does not disclose or render obvious the “the semiconductor die has a lateral sidewall that extends between the first and second sides and an indent that extends into a portion of the lateral sidewall and to the first side; and the electrical isolation coating layer extends along the indent and on the first side.” When combined with all other limitations of base claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899