DETAILED ACTION
This office action is in response to the election of claims filed on March 9, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
Applicant's election of claims filed on March 9, 2026, in response to the office action mailed on January 20, 2026 are acknowledged. The present office action is made with all the suggested arguments being fully considered.
Applicant's election with traverse of Claims 1-14 in the reply filed on March 9, 2026 is acknowledged. The traversal is on the ground(s) that “The species are not 'independent' under MPEP § 802.01; they are 'related' because they share a common functional purpose: providing a power-efficient chip-scale package (CSP) using selective polyimide. Because they are related, the Examiner must prove both (1) that they are patentably distinct AND (2) that there is an undue burden. The Examiner has failed to satisfy both prongs. Additionally, MPEP § 803 and MPEP § 806 state that for a restriction to be proper, the inventions must be independent or distinct as claimed. Since "claims themselves are never species" but rather define the embodiments (species), the Examiner must show how the claims are limited to those different embodiments. This is not found persuasive.
As set forth in the restriction requirement mailed on 01/20/2026, the examiner set forth that the application contained several species including mutually exclusive characteristics.
Figs. 10a-11c, for example illustrates a semiconductor package (e.g., a power wafer chip scale package) comprising the following features: an electronic component electrically connecting metal post to conductive terminals through wire bonding. These features, however, are not present and/or illustrated in Fig. 1-9c. Figs. 7a-9c, for example illustrates a semiconductor package comprising the following features: an electronic component electrically connected to conductive terminals through metal posts bonded between the electronic component active surface and a top surface of the conductive terminals. These features, however, are not present and/or illustrated in Fig. 1-6e and 10a-11c.
Accordingly, the figures contained in Species 1, Species 2, Species 3 and Species 4, at the very least, are not obvious variants of each other and they illustrate devices with different features, and therefore the unpatentability of one species would not necessarily imply the unpatentability of the other species. Because of the above, and because the applicant failed to distinctly and specifically point out that the species are not patentably distinct (emphasis added), and did not present evidence or identify evidence on record showing the species to be obvious variations of one another, the requirement is still deemed proper and is, therefore, made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 11, 2023 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It is unclear to the examiner what the applicant is claiming in claim 2, reciting “wherein the semiconductor package includes a substrate having first and second vias extending through the substrate, the first via having a larger diameter than the second via.” In preceding claim 1, the following limitations are recited “a semiconductor die having a device side with circuitry formed therein; a passivation layer abutting the device side; first and second vias coupling to the device side and extending through the passivation layer.”
However, claim 2 states “wherein the semiconductor package includes a substrate having first and second vias extending through the substrate, the first via having a larger diameter than the second via.” Therefore, the examiner raises the question as to which “first via having a larger diameter than the second via” as there are two sets of first and second vias provided in the claims. As a result, the claim is considered ambiguous. Appropriate correction is required. For purpose of examination, the examiner has interpreted claim 2 to read “wherein the semiconductor package, includes a substrate having a set of third vias extending through the substrate, the set of third vias having a larger diameter than the first and second vias.”
Claims 3-4, depend from Claim 2, thus inherit the deficiencies identified supra. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi (US 2005/0205993) in view of Lin (US 2019/0164860)
With respect to Claim 1, Yamaguchi discloses (Fig. 1B) most aspects of the current invention including a semiconductor package (100), comprising:
a semiconductor die (12) having a device side (bottom side) with circuitry formed therein;
a passivation layer (15/16) abutting the device side;
first and second vias (vertical vias 18) coupling to the device side and extending through the passivation layer, the first and second vias having diameters ranging from 0.5 microns to 10 microns;
first and second metal layers (horizontal metal portions 18) coupled to the first and second vias, respectively, the first and second metal layers abutting the passivation layer and having thicknesses in the range of 4 microns to 25 microns;
an insulation layer (30) abutting the first and second metal layers and separating the first and second metal layers, the insulation layer having an orifice (openings in insulating layer 30) in vertical alignment with the second metal layer;
a third metal layer (metal portions 20) coupled to the second metal layer through the orifice and having a thickness ranging from 10 microns to 80 microns, the third metal layer vertically aligned with the first and second metal layers;
a conductive member (conductive member 244) coupled to the third metal layer by way of a solder member (solder 246), the solder member having a thickness ranging from 10 microns to 80 microns;
a mold compound covering the semiconductor die, the passivation layer, the first and second vias, the first, second, and third metal layers, the insulation layer, the solder member, and at least part of the conductive member
However, Yamaguchi does not show wherein the first and second vias having diameters ranging from 0.5 microns to 10 microns, the first and second metal layers having thicknesses in the range of 4 microns to 25 microns, the third metal layer having a thickness ranging from 10 microns to 80 microns, the solder member having a thickness ranging from 10 microns to 80 microns and a mold compound covering the semiconductor die, the passivation layer, the first and second vias, the first, second, and third metal layers, the insulation layer, the solder member, and at least part of the conductive member.
On the other hand, and in the same field of endeavor, Lin teaches (Fig 17) a semiconductor package, comprising a semiconductor die (50A) having a device side (bottom side) with circuitry formed therein, a passivation layer abutting the device side, first and second vias coupling to the device side and extending through the passivation layer, first and second metal layers coupled to the first and second vias, an insulation layer abutting the first and second metal layers, a third metal layer coupled to the second metal layer, a conductive member coupled to the third metal layer by way of a solder member, and further comprising a mold compound (110) covering the semiconductor die, the passivation layer, the first and second vias, the first, second, and third metal layers, the insulation layer, the solder member, and at least part of the conductive member. Lin uses the mold compound is used to protect the device from external damage.
Therefore, one of ordinary skill in the art would have known that mold compound are typically used in the semiconductor packaging industry to provide protection to the device from external damage.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate a mold compound covering the semiconductor die, the passivation layer, the first and second vias, the first, second, and third metal layers, the insulation layer, the solder member, and at least part of the conductive member in the device of Yamaguchi, because mold compounds are well-known in the semiconductor packaging industry to provide protection to the device from external damage, as suggested by Lin, and implementing the mold compound for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
However, it is noted that the specification fails to provide teachings about the criticality of the thickness of the first and second vias, the thickness of the first and second metal layers, the thickness of the third metal layer, and the thickness of the solder member.
Regarding claim 1, the courts have held that differences in the thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thickness and similar thickness are known in the art (see e.g. Lin), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Yamaguchi and Lin.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 2, Lin teaches (Fig 17) wherein the semiconductor package, includes a substrate having a set of third vias (74) extending through the substrate, the set of third vias having a larger diameter than the first and second vias.
With respect to Claim 3, Lin teaches the set of third vias having a larger diameter than the first and second vias.
However, it is noted that the specification fails to provide teachings about the criticality of the thickness of the first and second vias.
Regarding claim 3, the courts have held that differences in the thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thickness and similar thickness are known in the art (see e.g. Lin), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Yamaguchi and Lin.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 4, Lin teaches (Fig 17) wherein the substrate is a ball grid array (BGA) substrate.
With respect to Claim 6, Lin teaches (Fig 17) wherein further comprising a fourth metal layer co-planar with the first and second metal layers, and fourth metal layer having a segment positioned between the first and second metal layers, the fourth metal layer representing a different electrical node than the first and second metal layers.
With respect to Claim 7, Lin teaches (Fig 17) wherein the first and second metal layers share an electrical node.
With respect to Claim 9, Yamaguchi discloses (Fig. 1B) wherein the insulation layer includes a second orifice through which the third metal layer is coupled to the first metal layer.
With respect to Claim 10, Yamaguchi discloses (Fig. 1B) wherein the orifice (openings in insulating layer 30) has a non-circular horizontal cross-sectional shape.
Regarding claim 10, the courts have held that differences in the dimensions will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimensions are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the dimensions and similar dimensions are known in the art (see e.g. Yamaguchi), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Yamaguchi and Lin.
Criticality: The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi (US 2005/0205993) in view of Lin (US 2019/0164860) and in further view of Tuncer (US 11,538,738)
With respect to Claim 5, Yamaguchi in view of Lin discloses most aspects of the present invention. However, the combination of references do not show wherein the package is a quad flat no lead (QFN) package, and wherein the conductive member is a lead of the QFN package.
On the other hand, and in the same field of endeavor, Tuncer teaches (Fig 8) a semiconductor package, comprising a semiconductor die (310) having a device side with circuitry formed therein, and a mold compound (650) covering the semiconductor die, wherein the package is a quad flat no lead (QFN) package, and wherein a conductive member (811) is a lead of the QFN package. Tuncer teaches QFN packages are increasingly used because the no-leads packages require less board area than leaded packages (column 5 lines 62-64).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the package is a quad flat no lead (QFN) package, and wherein the conductive member is a lead of the QFN package in the device of Yamaguchi and Lin, as taught by Tuncer because QFN packages are increasingly used because the no-leads packages require less board area than leaded packages.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi (US 2005/0205993) in view of Lin (US 2019/0164860) and in further view of Shibuya (US 2023/0038411)
With respect to Claim 8, Yamaguchi in view of Lin discloses most aspects of the present invention. However, the combination of references do not show wherein the package is a small outline transistor (SOT) package.
On the other hand, and in the same field of endeavor, Shibuya teaches (Fig 3A) a semiconductor package, comprising a semiconductor die (306) having a device side with circuitry formed therein, and a mold compound (119) covering the semiconductor die, wherein the package is a small outline transistor (SOT) package. Shibuya teaches a small outline transistor (SOT) package is a cost-effective way to help prevent mold flash, and is an example of the highest unit density leadframe strip (or leadframe panel) design semiconductor package to result in a higher unit density design and a decrease in the needed mold clamp force per unit (par 8).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the package is a small outline transistor (SOT) package in the device of Yamaguchi and Lin, as taught by Shibuya, because a small outline transistor (SOT) package is a cost-effective way to help prevent mold flash, and is an example of the highest unit density leadframe strip (or leadframe panel) design semiconductor package to result in a higher unit density design and a decrease in the needed mold clamp force per unit.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang (US 2019/0035752) in view of Lin (US 2019/0164860).
With respect to Claim 11, Chuang discloses (Fig. 3C) most aspects of the current invention including a power wafer chip scale package (WCSP), comprising:
a semiconductor die (110) having a device side (bottom side) with circuitry formed therein
a passivation layer (140) abutting the device side
first (132), second (134), and third vias (150) coupled to the device side and extending through the passivation layer
first (412a), second (412b), and third (418) metal layers coupled to the first, second, and third vias, respectively, the first, and second, and third metal layers abutting the passivation layer, the second metal layer between the first and third metal layers
an insulation layer (414) abutting the first, second, and third metal layers and separating the first, second, and third metal layers from each other, the insulation layer having orifices vertically aligned with the first and third metal layers but not with the second metal layer
a fourth metal layer (422a) coupled to the first and third metal layers through the orifices and not coupled to the second metal layer, the fourth metal layer vertically aligned with the first, second, and third metal layers
However, Chuang does not show wherein the fourth metal layer having a horizontal diameter ranging from 40 microns to 2000 microns.
On the other hand, and in the same field of endeavor, Lin teaches (Fig 17) a semiconductor package, comprising a semiconductor die (50A) having a device side (bottom side) with circuitry formed therein, a passivation layer abutting the device side, first and second vias coupling to the device side and extending through the passivation layer, first and second metal layers coupled to the first and second vias, an insulation layer abutting the first and second metal layers, a third metal layer coupled to the second metal layer, a conductive member coupled to the third metal layer.
However, it is noted that the specification fails to provide teachings about the criticality of the fourth metal layer having a horizontal diameter ranging from 40 microns to 2000 microns.
Regarding claim 11, the courts have held that differences in the diameters will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such diameters are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the diameters and similar diameters are known in the art (see e.g. Lin), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Chuang and Lin.
Criticality: The specification contains no disclosure of either the critical nature of the claimed diameters or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Allowable Subject Matter
Claims 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached M-F 9AM-4PM.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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