DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 14-15, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kyozuka (US 2019/0013263).
Regarding claim 1, fig. 9C of Kyozuka discloses a substrate 1, comprising: an electronic component 41 including a lower planar surface having one or more electronic component terminals 42, a core 10 having an upper planar surface (top of 15) facing the lower planar surface (bottom of 41) of the electronic component 41; a patterned metallization layer 12a over the upper planar surface (top of 15) of the core 10, wherein the patterned metallization layer 12a is connected to the one or more electronic component terminals 42 at the lower planar surface (bottom of 41) of the electronic component 41; one 21 or more dielectric layers 21 disposed over the upper planar surface (top of 15) of the core 10; and a cavity 21x formed within the one 21 or more dielectric layers that exposes the patterned metallization layer 12a and a portion of the upper planar surface of the core (top of 15) such that the one or more electronic component terminals 42 are connected 50 to the exposed patterned metallization layer 12a and the electronic component 41 is located in the cavity 21x and over the upper planar surface (top of 15) of the core 10.
Regarding claim 2, fig. 9C of Kyozuka discloses that the substrate 1 further comprises: one or more vias 22a electrically connected to the patterned metallization layer 12 and extending through the one 21 or more dielectric layers; and one or more metal terminals 22b connected to the one or more vias 22a, wherein the one or more metal terminals 22b are configured to provide one or more electrical connections 22b to an electronic package mounted to the substrate 1.
Regarding claim 3, fig. 9C of Kyozuka discloses a filler 30 disposed in regions between sidewalls 21x of the one 21 or more dielectric layers and sidewalls (“a gap may be provided between the inner wall surfaces of the openings 21x and 23x and the side surface of the semiconductor chip 40“, par [0084]) of the electronic component 41.
Regarding claim 4, fig. 9C of Kyozuka discloses that the filler 30 comprises a dielectric (“insulation resin“, par [0087]) material 30.
Regarding claim 5, fig. 9C of Kyozuka discloses that the dielectric material of the filler 30 comprises a same dielectric material (“insulation resin”, par [0027]) as the one or more dielectric layers 21.
Regarding claim 7, fig. 9C of Kyozuka discloses a non-conductive paste 30 disposed in the cavity between the lower planar surface (bottom of 41) of the electronic component 41 and the upper planar surface (top of 15) of the core 10.
Regarding claim 8, fig. 9C of Kyozuka discloses that the non-conductive paste 30 at least partially surrounds (“a gap may be provided between the inner wall surfaces of the openings 21x and 23x and the side surface of the semiconductor chip 40“, par [0084]) one or more sidewalls of the electronic component 41.
Regarding claim 9, fig. 9C of Kyozuka discloses that the one or more electronic component terminals 42 are electrically connected to the patterned metallization layer 12a by one or more electrical paths 50 comprising one or more solder connections (“solder bumps”, par [0086]).
Regarding claim 14, fig. 9C of Kyozuka discloses that the core 10 has a thickness greater (10 taller than 41) than a height of the electronic component 41.
Regarding claim 15, fig. 9C of Kyozuka discloses that the one or more dielectric layers (23, 21) include a plurality of dielectric layers (23, 21) having further patterned metallization layers 22b respectively disposed over each dielectric layer 21 of the plurality of dielectric layers 21.
Regarding claim 17, fig. 9C of Kyozuka discloses an electronic device 1, comprising: a substrate 1 including, an electronic component 41 including a lower planar surface having one or more electronic component terminals 42, a core 10 having an upper planar surface (top of 15) facing the lower planar surface (bottom of 41) of the electronic component 41; a patterned metallization layer 12a over the upper planar surface of the core 10, wherein the patterned metallization layer 12a is connected to the one or more electronic component terminals 42 at the lower planar surface of the electronic component 41; one 21 or more dielectric layers disposed over the upper planar surface (top of 15) of the core 10;and a cavity 21x formed within the one 21 or more dielectric layers, wherein the one 21 or more dielectric layers expose the patterned metallization layer 12a and a portion of the upper planar surface (top of 15) of the core 10 such that the one or more electronic component terminals 41 are connected to the exposed patterned metallization layer 12a and, wherein the electronic component 41 is located in the cavity 21x and over the upper planar surface (top of 15) of the core 10.
Regarding claim 19, fig. 9C of Kyozuka discloses an electronic circuit package (“semiconductor package”, par [0043]) mounted on the substrate 1 and electrically connected to the one or more electronic component terminals 12.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kyozuka (US 2019/0013263) in view of Tezak (US 2010/0282498).
Regarding claim 6, Kyozuka does not disclose that the patterned metallization layer is disposed on the upper planar surface of the core.
However, fig. 3 of Tezak discloses that the patterned metallization layer (circuit traces under “flip-chip bonding”, par [0031]) disposed on the upper planar surface (top of core layer 9) of the core 9.
Therefore, it would have been obvious to one of ordinary skill in the art to form the electrode pad of Kyozuka on the core layer of Tezak in order to embed semiconductor devices in a multilayer circuit board. See par [0015] of Tezak.
Regarding claim 20, Kyozuka does not disclose that the electronic device comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle.
However, fig. 15 of Tezak disclose that the electronic device 1500 comprises at least one of: a music player (“music player”, par [0098]), a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle.
Therefore, it would have been obvious to one of ordinary skill in the art to form the semiconductor package of Kyozuka with a music player as taught in Tezak in order to play music. See par [0098] of Tezak.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kyozuka (US 2019/0013263) in view of Hashino (US 2021/0249374).
Regarding claim 10, fig. 9C of Kyozuka discloses that the one or more electronic component terminals 42 are electrically connected to the patterned metallization layer 12a by one or more electrical paths 50, providing a metallurgical bond between the one or more electronic component terminals 42 and the patterned metallization layer 12a.
Kyozuka does not disclose the connection portion formed of one or more thermocompression bonds.
However, Hashino disclose the connection portion (“pillar bumps”, par [0002]) formed of one or more thermocompression bonds (“thermocompression bonding”, par [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the connection portion of Kyozuka with the thermocompression bonding as taught in Hashino in order to provide a method of mounting the chip on the substrate. See par [0002] of Hashino.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kyozuka (US 2019/0013263) in view of Paital (US 2023/0085411).
Regarding claim 11, Kyozuka does not discloses that the core has a thickness that is greater than about 760 micrometers.
However, fig. 1 of Paital discloses that the core 104 has a thickness that is greater than about 760 micrometers (“1500 micrometer”, par [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the core of Kyozuka with the thickness as taught in Paital in order to provide a rigid substrate. See par [0066] of Paital.
Regarding claim 12, Kyozuka does not disclose that the core has a thickness that is greater than about 820 micrometers.
However, fig. 1 of Paital discloses that the core 104 has a thickness that is greater than about 820 micrometers (“1500 micrometer”, par [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the core of Kyozuka with the thickness as taught in Paital in order to provide a rigid substrate. See par [0066] of Paital.
Regarding claim 13, Kyozuka does not discloses that the core has a thickness that is greater than about 1240 micrometers.
However, fig. 1 of Paital discloses that the core has a thickness that is greater than about 1240 micrometers (“1500 micrometer”, par [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the core of Kyozuka with the thickness as taught in Paital in order to provide a rigid substrate. See par [0066] of Paital.
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kyozuka (US 2019/0013263) in view of Kim et al. (US 2021/0273042) (“Kim”).
With regard to claims 16, Kyozuka does not disclose that the electronic component comprises a deep trench capacitor.
However, fig. 1 of Kim discloses that that the electronic component 170 comprises a deep trench capacitor (“deep trench capacitors 170”, par [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the semiconductor substrate of Kyozuka with as a deep trench capacitor as taught in Kim in order to provide larger capacitors and higher capacitance. See par [0061] of Kim.
With regard to claims 18, Kyozuka does not disclose that the electronic component comprises a deep trench capacitor.
However, fig. 1 of Kim discloses that that the electronic component 170 comprises a deep trench capacitor (“deep trench capacitors 170”, par [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the semiconductor substrate of Kyozuka with as a deep trench capacitor as taught in Kim in order to provide larger capacitors and higher capacitance. See par [0061] of Kim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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