DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 21-30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected 21-30, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/28/2025.
Applicant’s election without traverse of claims 1-20 in the reply filed on 11/28/2025 is acknowledged.
Claim Rejections - 35 USC § 112
Claims 3-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 3 ll. 2, it is indefinite as to whether the sidewall of the core refers to an outer sidewall or an inner sidewall of the core. For purposes of examination the former interpretation will be used. Claims 4-5 do not clear up the indefinite limitation in claim 3.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10, 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2007/0025092) (“Lee”).
With regard to claim 1, fig. 2g of Lee discloses a substrate 10, comprising: an electronic component 25 including a lower planar surface (bottom of 25) having one or more electronic component terminals 27a, a core 13 having an upper planar surface (top of 13) facing the lower planar surface (bottom of 25) of the electronic component 25; a patterned metallization layer 27b over the upper planar surface (top of 13) of the core 13, wherein the patterned metallization layer 27b is connected to the one or more electronic component terminals 27a at the lower planar surface of the electronic component 25; one or more dielectric layers 16 disposed over the upper planar surface (top of 13) of the core 13; and a cavity 17 formed within the one or more dielectric layers 16, wherein the electronic component 25 is located in the cavity 17 and over the upper planar surface (top of 13) of the core 13.
With regard to claim 2, fig. 2g of Lee discloses that the substrate 10 further comprises: one or more vias 21 electrically connected to the patterned metallization layer 24b and extending through the one or more dielectric layers 16; one or more metal terminals 27 connected to the one or more vias 21, wherein the one or more metal terminals 27 are configured to provide one or more electrical connections 27 to an electronic package 25 mounted to the substrate 10.
With regard to claim 3, fig. 2g of Lee discloses that a filler 26 disposed in regions between sidewalls (sidewall of 13) of the core 2 and sidewalls of the electronic component 25.
With regard to claim 4, fig. 2g of Lee discloses that the filler 26 comprises a dielectric material (“encapsulation material “, par [0022]).
With regard to claim 5, fig. 2g of Lee discloses that the dielectric material of the filler (build-up layers 16 around the capacitor 22) comprises a same dielectric material 16 as the one or more dielectric layers 16.
With regard to claim 6, fig. 2g of Lee discloses that the patterned metallization layer 27b is disposed on the upper planar surface (top of 13) of the core 13.
With regard to claim 7, fig. 2g of Lee discloses that a non-conductive paste 28 disposed in the cavity 17 between the lower planar surface (bottom of 25) of the electronic component 25 and the upper planar surface (top of 13) of the core 13.
With regard to claim 8, fig. 2g of Lee discloses that the non-conductive paste 26 at least partially surrounds one or more sidewalls of the electronic component 25.
With regard to claim 10, fig. 2g of Lee discloses that the one or more electronic component terminals 25 are electrically connected to the patterned metallization layer 27b by one or more electrical paths 27 having one or more thermocompression bonds 27 providing a metallurgical bond between the one or more electronic component terminals 27b and the patterned metallization layer 27b.
With regard to claim 15, fig. 2g of Lee discloses that the one or more dielectric layers 16 include a plurality of dielectric layers 16 having further patterned metallization layers (“conductive traces 21”, par [0022]) respectively disposed over each dielectric layer 16 of the plurality of dielectric layers 16.
With regard to claim 17, fig. 2g of Lee discloses an electronic device 10, comprising: a substrate 10 including, an electronic component 25 including a lower planar surface having one or more electronic component terminals 27a, a core 13 having an upper planar surface facing the lower planar surface of the electronic component 25;a patterned metallization layer 27b over the upper planar surface of the core 13, wherein the patterned metallization layer 27b is connected to the one or more electronic component terminals 27a at the lower planar surface of the electronic component 25;one or more dielectric layers 16 disposed over the upper planar surface of the core 13; and a cavity 17 formed within the one or more dielectric layers 16, wherein the electronic component 25 is located in the cavity 17 and over the upper planar surface of the core 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2007/0025092) (“Lee”) in view of Eeton et al. (US 2024/0170351) (“Eeton”).
With regard to claim 9, fig. 2g of Lee discloses that the one or more electronic component terminals 27a are electrically connected to the patterned metallization layer 24b by one or more electrical paths 27.
Lee does not disclose that the one or more electronic component terminals are one or more solder connections.
However, fig. 9 of Eeton discloses that the one or more electronic component terminals 854 are one or more solder connections (“solder contacts in the solder 852”, par [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the interconnects of Lee with the solder contacts as taught in Eeton in order to provide an electrical connection between the embedded component and conductive traces. See par [0050] of Eeton.
With regard to claim 11, Lee does not disclose that the core has a thickness that is greater than about 760 micrometers.
However, fig. 9 of Eeton discloses that the core 202 has a thickness that is greater than about 760 micrometers (“1 millimeter”, par [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the core of Lee with the thickness of 1 millimeter as taught in Eeton in order to provide a glass core. See par [0029] of Eeton.
With regard to claim 12, Lee does not disclose that the core has a thickness that is greater than about 820 micrometers.
However, fig. 9 of Eeton discloses that the core 202 has a thickness that is greater than about 820 micrometers (“1 millimeter”, par [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the core of Lee with the thickness of 1 millimeter as taught in Eeton in order to provide a glass core. See par [0029] of Eeton.
With regard to claim 13, Lee does not disclose that the core has a thickness that is greater than about 1240 micrometers.
However, fig. 9 of Eeton discloses that the core 202 has a thickness that is greater than about 1240 micrometers (“1 millimeter”, par [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the core of Lee with the thickness of 1 millimeter as taught in Eeton in order to provide a glass core. See par [0029] of Eeton.
Claims 14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2007/0025092) (“Lee”) in view of Kim et al. (US 2021/0273042) (“Kim”).
With regard to claim 14, Lee does not disclose that the core has a thickness greater than a height of the electronic component.
However, fig. 1 of Kim discloses that the core 132 has a thickness greater than a height of the electronic component 170.
Therefore, it would have been obvious to one of ordinary skill in the art to form the core of Lee with the thickness as taught in Kim in order to provide the mechanical strength to the IC package. See par [0031] of Kim.
With regard to claims 16 and 18, Lee does not disclose that the electronic component comprises a deep trench capacitor.
However, fig. 1 of Kim discloses that that the electronic component 170 comprises a deep trench capacitor (“deep trench capacitors 170”, par [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the capacitors of Lee as a deep trench capacitor as taught in Kim in order to provide larger capacitors and higher capacitance. See par [0061] of Kim.
With regard to claim 19, fig. 2g of Lee does not discloses comprising: an electronic circuit package mounted on the substrate and electrically connected to the one or more electronic component terminals.
However, fig. 1 of Kim discloses an electronic circuit package 110 mounted on the substrate 130 and electrically connected to the one or more electronic component terminals 171D.
Therefore, it would have been obvious to one of ordinary skill in the art to form the package of Lee with the IC and dep trench capacitor as taught in Kim in order to arrange the deep trench capacitor close to the circuit of the IC to reduce the amount of added inductance. See par [0037] of Kim.
With regard to claim 20, fig. 2g of Lee discloses that the electronic device 10 comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone (“Cell phones”, par [0002]), a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle.
Conclusion
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893