DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on June 5, 2026 with respect to 35 USC § 112 (b) rejection of claim 2 and to the 35 USC § 102 rejections using Kim and Bae references are persuasive. These rejections have been withdrawn. However, upon further search and considerations, the amended claims read into the 35 USC § 103 rejection using Bae in view of Civay.
In summary, the application is not in a condition of an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 6 and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Bae (US 2022/0108921 A1) in view Civay (US 2019/0220567 A1), as evidenced by Yamano (WO 2018/225571 A1; see FOR and NPL mailed on 08 April 2026 for foreign document and English translation) and Chen (US 2022/0293607 A1).
Regarding claim 1, Bae teaches a metal wiring of a semiconductor device (Fig. 12), comprising:
first metal lines (204S1 & 204S2 & 204S3 & each respective segment of 205S) spaced apart from each other and disposed in a first metal layer (220 & 230 & 231 & 204 & 205S; see ¶ [0041]), each of the first metal lines having an opening (T4 & T5) in a heat-concentrated region (¶ [0059]: the region of T4 & T5 is where the first metal lines contact 201; as evidenced by Yamano, see Fig. 2 and ¶ [0103] of the English translation, a region where two wiring layers, 2 & 52, contact each other is a heat-concentrating region);
a dielectric material (air is a dielectric as evidenced by Chen, see ¶ [0042] and claim 9) disposed in the opening; and
a contact metal (201) passing through a dielectric layer (210, see ¶ [0042] ) beneath the first metal layer, the contact metal crossing the first metal lines (as shown in Fig. 12, 201 crosses the metal lines in a perpendicular direction), connecting the first metal lines to each other (as shown in Fig. 12), and connected to the first metal lines around the opening (as shown in Fig. 12).
However, Bae does not teach the first metal lines being parallel to each other and spaced apart from each other in a plan view, wherein the heat-concentrated region is where the first metal lines and the contact metal cross each other from the plan view.
Civay, in the same field of invention, teaches a device wherein first metal lines (140; see Fig. 13 and ¶ [0048] ) are being parallel to each other and spaced apart from each other in a plan view (¶ [0048]: Fig. 13 is a top view), wherein the heat-concentrated region is where the first metal lines and the contact metal cross each other from the plan view (since Bae teaches contact metal crossing the first metal lines in a perpendicular direction, then Bae in view of Civay teaches this limitation).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Civay into the device of Bae to arrange the first metal lines to be in parallel to each other and spaced apart from each other in a plan view, thereby making the contact metal cross the first metal line in the plan view. The ordinary artisan would have been motivated to modify Bae in the manner set forth above for at least the purpose of improving and optimizing the minimum spacing requirements of vias while maintaining other desired design parameters (Civay ¶ [0048] ), thereby increasing the product yields and reducing defects (¶ [0038] ).
Regarding claim 3, the metal wiring of a semiconductor device according to claim 1, wherein the contact metal has a line shape (Bae Fig. 12 shows 201 extends horizontally, with the top surface of 201 having a line shape) when viewed from the plan view (Bae in view of Civay teaches this) .
Regarding claim 6, Bae teaches a metal wiring of a semiconductor device (Fig. 12), comprising:
first metal lines (204S1 & 204S2 & 204S3 & each respective segment of 205S) spaced apart from each other and disposed in a first metal layer (220 & 230 & 231 & 204 & 205S; see ¶ [0041]), each of the first metal lines disconnected in a heat-concentrated region (¶ [0059]: the region of T4 & T5 is where the first metal lines contact 201; as evidenced by Yamano, see Fig. 2 and ¶ [0103] of the English translation, a region where two wiring layers, 2 & 52, contact each other is a heat-concentrating region);
a dielectric material (air is a dielectric as evidenced by Chen, see ¶ [0042] and claim 9) disposed in the heat-concentrated region; and
a contact metal (201) passing through a first dielectric layer (210, see ¶ [0042] ) beneath the first metal layer, the contact metal crossing the first metal lines in the heat-concentrated region in a vertical direction (the top surface of 201 crosses the first metal line in a perpendicular direction when viewed from the top), connecting the first metal lines to each other (as shown in Fig. 12), and electrically connecting disconnected ends (bottom ends of 204S1, 204S2, and 204S3 are disconnected by trenches T4 and T5) of each of the first metal lines (each bottom end is connected to 201 through their respective barrier metal patterns 205S).
However, Bae does not teach the first metal lines being parallel and spaced apart from each other in a plan view, wherein the contact metal crossing the first metal lines as seen from the plan view.
Civay, in the same field of invention, teaches a device comprising first metal lines (140; see Fig. 13 and ¶ [0048] ) being parallel to and spaced apart from each other in a plan view (¶ [0048]: Fig. 13 is a top view), wherein the contact metal crossing the first metal lines as seen from the plan view (since Bae teaches contact metal crossing the first metal lines in a perpendicular direction, then Bae in view of Civay teaches this limitation).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Civay into the device of Bae to arrange the first metal lines to be in parallel to each other and spaced apart from each other in a plan view, thereby making the contact metal cross the first metal line in the plan view. The ordinary artisan would have been motivated to modify Bae in the manner set forth above for at least the purpose of optimizing the minimum spacing requirements of vias while maintaining other desired design parameters (Civay ¶ [0048] ), thereby increasing the product yields and reducing defects (¶ [0038] ).
Regarding claim 11, the metal wiring of a semiconductor device according to claim 1, wherein a thickness (height of S024S1, S04S3, S04S2; se Bae Fig. 12) of each of the first metal lines is uniform (Fig 12 shows the height for each of these elements are the same).
Regarding claim 12, the metal wiring of a semiconductor device according to claim 11, wherein the thickness of each of the first metal lines is the same as a thickness (height of 220 & 230 & 231 & 204 & 205S that collectively encompasses the first metal line; Bae Fig. 12) of the first metal layer.
Regarding claim 13, the metal wiring of a semiconductor device according to claim 1, wherein the first metal lines are in direct contact (through each segment of 205S) with the contact metal (Bae Fig. 12 shows this).
Regarding claim 14, the metal wiring of a semiconductor device according to claim 6, wherein a thickness (height of S024S1, S04S3, S04S2; see Bae Fig. 12) of each of the first metal lines is uniform (Fig 12 shows the height for each of these elements are the same).
Regarding claim 15, the metal wiring of a semiconductor device according to claim 14, wherein a thickness (height of S024S1, S04S3, S04S2 & 205S; see Bae Fig. 12) of each of the first metal lines is the same as a thickness (collective height of 220 & 230 & 231 & 204 & 205S) of the first metal layer.
Regarding claim 16, the metal wiring of a semiconductor device according to claim 6, wherein the first metal lines are in direct contact (through each respective segment of 205S; see Bae Fig. 12) with the contact metal.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Bae (US 2022/0108921 A1) in view Civay (US 2019/0220567 A1) as applied to claim 1 above, and further in view of Kim ( US 2018/0261544 A1) as evidenced by Yamano (WO 2018/225571 A1; see FOR and NPL mailed on 08 April 2026 for foreign document and English translation).
Regarding claim 4, Bae in view of Civay teaches the metal wiring of a semiconductor device according to claim 1, but does not teach: wherein the heat-concentrated region is a region where the first metal layer does not overlap, in a vertical direction, a metal line disposed in a second metal layer.
Kim, in the same field of invention, teaches a semiconductor device (2000; see Fig. 25B), wherein the heat-concentrated region (AG1 are air gap regions where V1 and M1 contact each other, hence, as evidenced by Yamano ¶ [0103] , this is a heat-concentrating region) is a region where the first metal layer (V1) does not overlap, in a vertical direction (Z-axis), a metal line (left or middle M2) disposed in a second metal layer (LV3).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Bae in view of Civay to add a second metal layer, having a metal line, to the device such that the heat-concentration region where the first metal layer is located does not overlap, in a vertical direction, to the metal line in the second metal layer. The ordinary artisan would have been motivated to modify Bae in view of Civay in the manner set forth above for at least the purpose of using the metal line of the second metal layer as wiring interconnects to connect gate lines (GL see Fig. 25A and ¶ [0157]) of various transistors to via contacts (DV), for the further purpose of improving the device density and scalability (¶ [0003]).
Claims 5 and 7 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Bae (US 2022/0108921 A1) in view Civay (US 2019/0220567 A1), as evidenced by NPL: “Thermal Conductivity of Air, Ruthenium, and Molybdenum” (mailed on 08 April 2026).
Regarding claim 5, the metal wiring of a semiconductor device according to claim 1, wherein the dielectric material (air: 25.87 mW/m-K at 20 C, see evidence in NPL reference) that has a thermal conductivity lower than the first metal lines (Bae ¶ [0053]: 204 made of Ru or Mo; as evidenced by NPL, Ru: 116 W/m-K; Mo: 138 W/m-K ) is disposed in the opening.
Regarding claim 7, the metal wiring of a semiconductor device according to claim 6, wherein the dielectric material that has a thermal conductivity (as evidenced by NPL, air has a thermal conductivity of 25.87 mW/m-K at 20 C) lower than the first metal lines (Bae ¶ [0053]: 204 made of Ru or Mo; as evidenced by NPL, Ru: 116 W/m-K; Mo: 138 W/m-K ) is disposed between disconnected ends of the first metal lines (see Bae Fig. 12 shows air is disposed in T4 and T5).
Claims 8-10 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Bae (US 2022/0108921 A1) in view Civay (US 2019/0220567 A1) and Kim ( US 2018/0261544 A1) as evidenced by Yamano (WO 2018/225571 A1; see FOR and NPL mailed on 08 April 2026 for foreign document and English translation) and Chen (US 2022/0293607 A1).
Regarding claim 8, Bae teaches a metal wiring of a semiconductor device (Fig. 12), comprising:
first metal lines (204S1 & 204S2 & 204S3 & each respective segment of 205S) spaced apart from each other and disposed in a first metal layer (220 & 230 & 231 & 204 & 205S; see ¶ [0041]), each of the first metal lines disconnected (due to trenchesT4 & T5) in a heat-concentrated region (¶ [0059]: the region of T4 & T5 is where the first metal lines contact 201; as evidenced by Yamano, see Fig. 2 and ¶ [0103] of the English translation, a region where two wiring layers, 2 & 52, contact each other is a heat-concentrating region), and divided into a first part (204S1 & left 205S) and a second part (204S2 & right 205S);
a dielectric material (air is a dielectric as evidenced by Chen, see ¶ [0042] and claim 9) disposed in the heat-concentrated region; and
a contact metal (201) disposed beneath the first metal layer, the contact metal connecting the first part and the second part (see Fig. 12), crossing the first metal lines from the plan view (Fig. 12 shows 201 crossing the first metal lines when seen from above), connecting the first metal lines to each other (see Fig. 12) and disposed in a first dielectric layer (210) beneath the first metal layer.
However, Bae does not teach the first metal lines being parallel and spaced apart from each other in a plan view, wherein the contact metal crosses the first metal lines from the plan view.
Civay, in the same field of invention, teaches a device wherein the first metal lines (140; see Fig. 13 and ¶ [0048]) are being parallel and spaced apart from each other from a plan view (¶ [0048]: Fig. 13 is a top view), wherein the contact metal crosses the first metal lines from the plan view (since Bae teaches contact metal crossing the first metal lines in a perpendicular direction, then Bae in view of Civay teaches this limitation).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Civay into the device of Bae to arrange the first metal lines to be in parallel to each other and spaced apart from each other in a plan view, thereby making the contact metal cross the first metal line in the plan view. The ordinary artisan would have been motivated to modify Bae in the manner set forth above for at least the purpose of optimizing the minimum spacing requirements of vias while maintaining other desired design parameters (Civay ¶ [0048] ), thereby increasing the product yields and reducing defects (¶ [0038] ).
However, Bae in view of Civay does not teach the device further comprising of a metal line of a second metal layer disposed in a vertical direction from a plan view, wherein the heat-concentration region is where the first metal line does not overlap with the metal of the second metal layer, and wherein a first distance in the vertical direction between the second metal layer and the contact metal is greater than a second distance between the second metal layer and the first metal layer.
Kim, in the same field of invention, teaches a device (2000; see Fig. 25B) comprising of a metal line (left or middle M2) of a second metal layer (LV3) disposed in a vertical direction (Z-axis) from a plan view (Kim Fig. 25A is a plan view),
wherein the heat-concentration region (AG1 in Fig. 25B are air gap regions where V1 and M1 contact each other; as evidenced by Yamano ¶ [0103] , this is a heat-concentrating region) is where the first metal line (V1) does not overlap with the metal of the second metal layer,
wherein a first distance (distance between LV3 and M1) in the vertical direction between the second metal layer and the contact metal (M1) is greater than a second distance (distance between layers LV3 and 1138) between the second metal layer and the first metal layer (layer 1138 contains V1).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Bae to add a second metal layer above the first metal layer, wherein the heat-concentration region is does not overlap a metal of the second metal layer in a vertical direction from a plan view, and wherein the second metal layer is located at a distance farther from the contact metal compared to the first metal layer. The ordinary artisan would have been motivated to modify Bae in view of Civay in the manner set forth above for at least the purpose of using the metal line of the second metal layer as wiring interconnects to connect gate lines (GL see Fig. 25A and ¶ [0157]) of various transistors to via contacts (DV), for the further purpose of improving the device density and scalability (¶ [0003]).
Regarding claim 9, the metal wiring of a semiconductor device according to claim 8, wherein a difference between the first distance and the second distance is the same as a thickness (vertical thickness of V1, see Kim Fig. 25B) of the first metal layer (as shown in Fig. 25B, the distance between M2 and M1 along the Z-axis is the same as the vertical thickness of V1).
Regarding claim 10, the metal wiring of a semiconductor device according to claim 8, wherein the contact metal has a line shape (Bae Fig. 12 shows 201 extends horizontally, with the top surface of 201 having a line shape) when viewed on a from the plan view.
Regarding claim 17, the metal wiring of a semiconductor device according to claim 8, wherein a thickness (height of S024S1, S04S3, S04S2 Bae Fig. 12) of each of the first metal lines is uniform (Fig 12 shows the height for each of these elements are the same).
Regarding claim 18, the metal wiring of a semiconductor device according to claim 17, wherein a thickness (height of S024S1, S04S3, S04S2 & 205S; see Bae Fig. 12) of each of the first metal lines is the same as a thickness (collective height of 220 & 230 & 231 & 204 & 205S) of the first metal layer.
Regarding claim 19, the metal wiring of a semiconductor device according to claim 8, wherein the first metal lines are in direct contact (through each respective segment of 205S; see Bae Fig. 12) with the contact metal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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