DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 04/16/2026 have been fully considered but they are not persuasive.
Applicant argues on pages 9 – 10 of the REMARKS, “Even if the Examiner's interpretation of the prior art resin fillers as "plugging inks" were accepted for the sake of argument, the cited combination fails to teach this structural placement. The Examiner alleges that Origuchi teaches this feature, asserting that the plugging ink extends below the lower surface of the electronic component. The Applicant respectfully submits that this is incorrect. Origuchi explicitly describes its filling step, noting that the liquid resin filler 92 is injected such that an end face at the core back surface 13 side of the resin filler 92 reaches levels of the core back surface 13 and the chip back surface 63 (Origuchi at 0077, "At the subsequent second filling step, the liquid resin filler 92 ... is injected again into the clearance between the internal wall surface of the housing hole 90 and the chip side surface 64 of the IC chip 61 by using the dispenser device. Consequently, the clearance between the housing hole 90 and the IC chip 61 is filled and the end face at the core back surface 13 side of the resin filler 92 reaches levels of the core back surface 13 and the chip back surface 63."). Thus, the resin filler sits perfectly flush with the bottom of the component. Subsequently, Origuchi teaches applying a photosensitive epoxy resin directly onto the core back surface 13 and the chip back surface 63 to carry out the exposure and the development so that the insulating layer 34 is formed (Origuchi at 0079, "Moreover, the photosensitive epoxy resin is applied onto the core back surface 13 and the chip back surface 63 to carry out the exposure and the development so that the insulating layer 34 is formed"). Therefore, the text of Origuchi proves that the lower dielectric layer (insulating layer 34) is formed directly on, and in direct physical contact with, the lower surface of the electronic component (chip back surface 63). In the cited art, no material extends between the electronic component and the lower dielectric layer; the ink only sits flush with the bottom of the component and never extends beneath it”. The Office respectfully disagrees. Firstly, note that the primary reference, Muramatsu, teaches where the ink is present between the lower surface of the component and the lower dielectric layer. Muramatsu also does not show any voids present in the ink, nor does not discuss presence of voids in the ink. Note also that the claim does not state, nor specify, that there are no voids between the lower surface of the embedded component and the lower dielectric layer. The claim states “a substantially void-free cured plugging ink partially surrounding the electronic component, the plugging ink extending between the inner sidewalls of the core defining the cavity and the plurality of external sidewalls of the electronic component and between the lower surface of the electronic component and an upper surface of the lower dielectric layer”. The claim states “comprising” a void-free cured plugging ink. The claim uses the term “substantially” which is a relative term that has not been quantitatively defined in the claim language to quantify a specific allowable amount of voids to be determined as “substantially void-free”. The claim also states the substantially void-free ink is “partially surrounding” the component and that the “ink extending” in part “between the lower surface of the electronic component and an upper surface of the lower dielectric layer”. The claim has not specified that defined voids are not present between a lower surface of the component and the upper surface of the lower dielectric layer. Applicant is arguing the teachings of Origuchi, however in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Muramatsu already teaches an ink, seemingly without voids, located between a lower surface of a component and a lower dielectric layer. Origuchi is shown teaching of a “void-free” ink. Origuchi also teaches that using a void-free ink provides filling a cavity and providing a reliable fill. Additionally it is obvious to one of ordinary skill in the art that a void-free ink would provide better adhesion between the component and the parts of the board around the component. Also see that Origuchi shows the presence of the ink between a lower surface of the component and the upper surface of a lower dielectric layer, in Origuchi’s Fig 14. Finally note that Origuchi (in Fig 1 as well as in Fig 14) discusses means to provide ink without voids, between an upper surface of an electronic component and an upper dielectric layer. Even if the Applicant is stating that Origuchi is only talking about void-free ink between other sides of a component, Origuchi is discussing of a substantially void-free ink, and that ink is partially surrounding the embedded component. Origuchi, in Fig 1, shows a void-free ink where the void-free ink is not only covering lateral sides of a component, but is also on a surface perpendicular to lateral sides of the component. That void-free ink is shown in Origuchi being on multiple surfaces of the embedded component, and Origuchi teaches of means to establish a void-free ink. The same ink, 92, is present in Figure 14 of Origuchi. Origuchi shows in Figure 14, all surfaces of the component being covered by the resin 92.
Applicant argues on page 11 of the REMARKS, “If a person of ordinary skill in the art were to modify these processes to allow material to flow underneath the component, as recited in the claims, the liquid resin would uncontrollably coat the electrodes and terminals in an uneven layer of insulating composite material. This modification would irreparably foul the electrical terminals, making the formation of the subsequent via connections technically impossible. It would completely defeat the entire purpose of the prior art's temporary tape sealing step. Because modifying the prior art to match the claimed structural placement would physically break the necessary electrical connections and render the prior art devices inoperable for their intended purpose, Muramatsu and Origuchi physically teach away from the claimed invention”. The Office respectfully disagrees. Origuchi does not specifically teach away from having a void-free ink between a lower surface of a component and an upper surface of a lower dielectric layer. As seen by Figure 1 of Origuchi, Origuchi teaches of a component 61 where a surface with terminals 65, the surface of 61 at 65, has filler 92 shown between the surface with 65 and a facing surface of another dielectric layer, 33. Origuchi in Fig 14 shows the same filler 92, present between the all facing component surfaces and all interfacing surfaces of the board. The structure shown in Figure 14 of Origuchi is similar to the assembly shown in Fig 1 of Muramatsu. Origuchi teaches of means to have a void-free ink and therefore shows, at the very least, the capability and benefits of having a void-free ink. In response to applicant's argument that “modifying the prior art to match the claimed structural placement would physically break the necessary electrical connections and render the prior art devices inoperable for their intended purpose, Muramatsu and Origuchi physically teach away from the claimed invention”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Note that the resin 92 is around the terminals 65 in Fig 1 of Origuchi, as well as in Figure 14.
Applicant argues on page 12 of the REMARKS, “The term "cured" structurally defines the physical state of the plugging ink in the final device as a hardened solid, which structurally and physically differs from an uncured, fluid, viscous, or liquid state. A cured solid possesses distinct, measurable physical and mechanical properties, such as rigidity, shape retention, and density, that a fluid or viscous substance inherently lacks. Therefore, the recitation of a "cured" ink imparts definite structural limitations to the claimed device and carries patentable weight”. The Office respectfully disagrees. As seen by Applicant’s Specification, [0038], the ink undergoes a “curing process”. Note that the claim has not quantified nor defined any “measurable physical and mechanical properties, such as rigidity, shape retention, and density”, as argued. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., physical or mechanical properties) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant argues on page 12 of the REMARKS, “The Applicant respectfully submits that these standard epoxy resin fillers fail to teach or suggest the specifically claimed "plugging ink."”. The Office respectfully disagrees. The Applicant has not defined nor specified any material(s) or composition(s) for the claimed “plugging ink”. As stated previously, the Office interprets ink as a fluid or viscous substance. The resin of Muramatsu and the resin of Origuchi are resins that are filled into a cavity through a dispenser and thus would have fluidity. As the material is not specified in the claim language, the current combination meets the current claim language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu (US 2011/0018099 A1) in view of Origuchi (US 2009/0237900 A1).
Regarding Claim 1, Muramatsu (US 2011/0018099 A1) discloses an electronic device (Fig 1-8), comprising: a substrate (10) comprising: a core (11-13) having an upper planar surface (upper surface of 12) and a lower planar surface (lower surface of 13), wherein the core (11-13) includes a cavity (90) extending between the upper planar surface (upper surface of 12) of the core (11-13) and the lower planar surface (lower surface of 13) of the core (11-13), the cavity (90) further being defined by inner sidewalls (sidewalls of 90) of the core (11-13); an electronic component (301) at least partially disposed in the cavity (90), the electronic component (301) including an upper planar surface (302) having one or more electronic component terminals (311,312), a lower surface (303), and a plurality of external sidewalls (306); a lower dielectric layer (34; [0094]) disposed over the lower planar surface (lower surface of 13) of the core (11-13) and below a lower planar surface (303) of the electronic component (301); a (substantially void-free cured) plugging ink (92; [0013,0063,0092] “epoxy resin” “charging step, by use of a dispenser apparatus (product of Asymtek), the resin filler 92 of a thermosetting resin (product of NAMICS CORPORATION) is charged into a gap between the accommodation hole”; as seen by Fig 7-8, 92 is shown as substantially without voids and plugging 90; note that the claim has not structurally defined this “ink” and is therefore being interpreted as a fluid or viscous substance as 92 is filling using a dispenser; https://www.dictionary.com/browse/ink; 92 is shown plugged/filled into a cavity 90) partially surrounding the electronic component (301), the plugging ink (92) extending between the inner sidewalls (side walls of 90) of the core (11-13) defining the cavity (90) and the plurality of external sidewalls (306) of the electronic component (301) and between the lower surface (303) of the electronic component (301) and an upper surface (upper surface of 34 in Fig 6) of the lower dielectric layer (34); and an upper metallization structure (41,43; [0064]) configured to provide one or more conductive paths ([0064,0074]) from the one or more electronic component terminals (311,312) to one or more upper metal terminals (41) of the upper metallization structure (41,43).
Though the claim uses the relative term of substantially, Muramatsu does not explicitly disclose substantially void-free plugging ink.
Origuchi (US 2009/0237900 A1) teaches of an electronic device (Fig 14), comprising: a substrate (10) comprising: a core (161,164; see Fig 3) having an upper planar surface (12) and a lower planar surface (13), wherein the core (161,164) includes a cavity (90) extending between the upper planar surface (12) of the core and the lower planar surface (13) of the core; an electronic component (61) at least partially disposed in the cavity (90), wherein the electronic component (61) is at least partially surrounded in the cavity (90) by a substantially void-free ([0077] “prevent a void”) (cured [0072-0078]) plugging ink (92;note that the claim has not structurally defined this “ink” and is therefore being interpreted as a fluid or viscous substance; https://www.dictionary.com/browse/ink; 92 is shown plugged/filled into a cavity), the electronic component (61) including an upper planar surface (62) having one or more electronic component terminals (65) and a lower surface (63), wherein the (cured [0072-0078]) plugging ink (92) extends below (see Fig 14 showing 92 spreading below 63; [0077-0079]) the lower surface (63) of the electronic component (61); and an upper metallization structure (41,43,23,24) configured to provide one or more conductive paths ([0061]) from the one or more electronic component terminals (65) to one or more upper metal terminals (24) of the upper metallization structure.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Muramatsu, comprising a substantially void-free plugging ink as taught by Origuchi, in order to fill the cavity and provide a reliable fill (Origuchi, [0077-0078]). Furthermore it would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Muramatsu, comprising a substantially void-free plugging ink as taught by Origuchi because removing voids would allow for better fixing of the component within the cavity, as a potentially remaining void would be a space where the resin filler would not be present and fixing of the filler, cavity wall and component wall would be depreciated with the presence of a void.
Claim states a “cured” but “cured” does not represent product structure but only refers to the process by which the ink is formed. Thus Claim is a product claim that recites a process step(s) of curing and is thus treated as a product-by-process claim. See MPEP2113.
Regarding Claim 12, Muramatsu discloses a substrate (Fig 1-8), comprising: a core (11-13) having an upper planar surface (upper surface of 12) and a lower planar surface (lower surface of 13), wherein the core (11-13) includes a cavity (90) extending between the upper planar surface (upper surface of 12) of the core (11-13) and the lower planar surface (lower surface of 13) of the core (11-13), the cavity (90) further being defined by inner sidewalls (sidewalls of 90) of the core (11-13); an electronic component (301) at least partially disposed in the cavity (90), the electronic component (301) including an upper planar surface (302) having one or more electronic component terminals (311,312), a lower surface (303), and a plurality of external sidewalls (306); a lower dielectric layer (34; [0094]) disposed over the lower planar surface (lower surface of 13) of the core (11-13) and below a lower planar surface (303) of the electronic component (301); a (substantially void-free cured) plugging ink (92; [0013,0063,0092] “epoxy resin” “charging step, by use of a dispenser apparatus (product of Asymtek), the resin filler 92 of a thermosetting resin (product of NAMICS CORPORATION) is charged into a gap between the accommodation hole”; as seen by Fig 7-8, 92 is shown as substantially without voids and plugging 90; note that the claim has not structurally defined this “ink” and is therefore being interpreted as a fluid or viscous substance as 92 is filling using a dispenser; https://www.dictionary.com/browse/ink; 92 is shown plugged/filled into a cavity 90) partially surrounding the electronic component (301), the plugging ink (92) extending between the inner sidewalls (side walls of 90) of the core (11-13) defining the cavity (90) and the plurality of external sidewalls (306) of the electronic component (301) and between the lower surface (303) of the electronic component (301) and an upper surface (upper surface of 34 in Fig 6) of the lower dielectric layer (34); and an upper metallization structure (41,43; [0064]) configured to provide one or more conductive paths ([0064,0074]) from the one or more electronic component terminals (311,312) to one or more upper metal terminals (41) of the upper metallization structure (41,43).
Though the claim uses the relative term of substantially, Muramatsu does not explicitly disclose substantially void-free plugging ink.
Origuchi (US 2009/0237900 A1) teaches of an electronic device (Fig 14), comprising: a substrate (10) comprising: a core (161,164; see Fig 3) having an upper planar surface (12) and a lower planar surface (13), wherein the core (161,164) includes a cavity (90) extending between the upper planar surface (12) of the core and the lower planar surface (13) of the core; an electronic component (61) at least partially disposed in the cavity (90), wherein the electronic component (61) is at least partially surrounded in the cavity (90) by a substantially void-free ([0077] “prevent a void”) (cured [0072-0078]) plugging ink (92;note that the claim has not structurally defined this “ink” and is therefore being interpreted as a fluid or viscous substance; https://www.dictionary.com/browse/ink; 92 is shown plugged/filled into a cavity), the electronic component (61) including an upper planar surface (62) having one or more electronic component terminals (65) and a lower surface (63), wherein the (cured [0072-0078]) plugging ink (92) extends below (see Fig 14 showing 92 spreading below 63; [0077-0079]) the lower surface (63) of the electronic component (61); and an upper metallization structure (41,43,23,24) configured to provide one or more conductive paths ([0061]) from the one or more electronic component terminals (65) to one or more upper metal terminals (24) of the upper metallization structure.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Muramatsu, comprising a substantially void-free plugging ink as taught by Origuchi, in order to fill the cavity and provide a reliable fill (Origuchi, [0077-0078]). Furthermore it would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Muramatsu, comprising a substantially void-free plugging ink as taught by Origuchi because removing voids would allow for better fixing of the component within the cavity, as a potentially remaining void would be a space where the resin filler would not be present and fixing of the filler, cavity wall and component wall would be depreciated with the presence of a void.
Claim states a “cured” but “cured” does not represent product structure but only refers to the process by which the ink is formed. Thus Claim is a product claim that recites a process step(s) of curing and is thus treated as a product-by-process claim. See MPEP2113.
Regarding Claim 16, Muramatsu further discloses the substrate (Fig 1-8) of claim 12, wherein the upper metallization structure (41,43) comprises: one or more metal vias (43; [0064]).
Claim(s) 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu (US 2011/0018099 A1) in view of Origuchi (US 2009/0237900 A1) as applied to claims 1 and 12 above, and further in view of Sakai (US 2012/0085572 A1).
Regarding Claim 2, Muramatsu in view of Origuchi teaches the limitations of the preceding claim.
Muramatsu does not disclose the electronic device of claim 1, wherein: the electronic component occupies at least 66% of the cavity.
Sakai (US 2012/0085572 A1) teaches of an electronic device (Fig 1), wherein: an electronic component (400) occupies at least 66% ([0036-0041]) of a cavity (200).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Muramatsu in view of Origuchi, wherein: the electronic component occupies at least 66% of the cavity as taught by Sakai, in order to meet usage requirements and control overall warpage effects on the device (Sakai, [0036-0041]).
Regarding Claim 13, Muramatsu in view of Origuchi teaches the limitations of the preceding claim.
Muramatsu does not disclose the substrate of claim 12, wherein: the electronic component occupies at least 66% of the cavity.
Sakai (US 2012/0085572 A1) teaches of an electronic device (Fig 1), wherein: an electronic component (400) occupies at least 66% ([0036-0041]) of a cavity (200).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate as taught by Muramatsu in view of Origuchi, wherein: the electronic component occupies at least 66% of the cavity as taught by Sakai, in order to meet usage requirements and control overall warpage effects on the device (Sakai, [0036-0041]).
Claim(s) 5, 7, 8, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu (US 2011/0018099 A1) in view of Origuchi (US 2009/0237900 A1) as applied to claims 1 and 16 above, and further in view of Suzuki (US 2013/0074332 A1).
Regarding Claim 5, Muramatsu in view of Origuchi teaches the limitations of the preceding claim.
Muramatsu further discloses the electronic device (Fig 1-8) of claim 1, further comprising: one or more vias (16) extending between the upper planar surface (upper surface of 12) of the core and the lower planar surface (lower surface of 13) of the core (11-13).
Muramatsu does not explicitly disclose the one or more vias are explicitly metal vias.
Suzuki (US 2013/0074332 A1) teaches of an electronic device (Fig 1-10), comprising: one or more metal vias (14) extending between an upper planar surface (12) of a core (11) and a lower planar surface (13) of the core.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Muramatsu in view of Origuchi, comprising metal vias as taught by Suzuki, in order to provide an electrically conductive material (Suzuki, [0036]).
Regarding Claim 7, Muramatsu in view of Origuchi and Suzuki teaches the limitations of the preceding claim, including metal via, and Muramatsu further teaches the electronic device (Fig1-8) of claim 5, wherein: at least one metal via (16) of the of the one or more metal vias (16) includes a metal via structure (16) having a hollow cavity (cavity comprising 17), wherein the hollow cavity of the metal via structure is filled with the (cured) plugging ink (17; [0057,0094] also “epoxy resin” 92 is also epoxy resin).
Claim states a “cured” but “cured” does not represent product structure but only refers to the process by which the ink is formed. Thus Claim is a product claim that recites a process step(s) of curing and is thus treated as a product-by-process claim. See MPEP2113.
Regarding Claim 8, Muramatsu in view of Origuchi and Suzuki teaches the limitations of the preceding claim.
Muramatsu further discloses the electronic device (Fig 1-8) of claim 7, wherein: the core (11-13) has a thickness above 800 micrometers ([0057]).
Regarding Claim 17, Muramatsu in view of Origuchi teaches the limitations of the preceding claim.
Muramatsu further discloses the substrate (Fig 1-8) of claim 16, wherein: at least one metal via (43) of the of the one or more metal vias includes a via structure (16) having a hollow cavity (cavity comprising 17), wherein the hollow cavity of the metal via structure is filled with the (cured) plugging ink (17; [0057,0094] also “epoxy resin” 92 is also epoxy resin).
Muramatsu does not explicitly disclose the one or more vias are explicitly metal vias such that the of the one or more metal vias includes a metal via structure having a hollow cavity, wherein the hollow cavity of the metal via structure is filled with the cured plugging ink.
Suzuki (US 2013/0074332 A1) teaches of an electronic device (Fig 1-10), comprising: one or more metal vias (14) extending between an upper planar surface (12) of a core (11) and a lower planar surface (13) of the core.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Muramatsu in view of Origuchi, comprising metal vias, such that the of the one or more metal vias includes a metal via structure having a hollow cavity, wherein the hollow cavity of the metal via structure is filled with the cured plugging ink as taught by Suzuki, in order to provide an electrically conductive material (Suzuki, [0036]).
Regarding Claim 18, Muramatsu in view of Origuchi and Suzuki teaches the limitations of the preceding claim.
Muramatsu further discloses the substrate (Fig 1-8) of claim 17, wherein: the core has a thickness above 700 micrometers ([0057]).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu (US 2011/0018099 A1) in view of Origuchi (US 2009/0237900 A1) and Suzuki (US 2013/0074332 A1) as applied to claim 5 above, and further in view of Sakai (US 2012/0085572 A1).
Regarding Claim 6, Muramatsu in view of Origuchi and Suzuki teaches the limitations of the preceding claim.
Muramatsu does not disclose the electronic device of claim 5, wherein: the core has a thickness equal to or less than 800 micrometers.
Sakai (US 2012/0085572 A1) teaches of a core (300) has a thickness equal to or less than 800 micrometers ([0036-0041]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Muramatsu in view of Origuchi and Suzuki, wherein: the core has a thickness equal to or less than 800 micrometers as taught by Sakai, in order to provide a thinner wiring board while still maintaining rigidity and control warpage (Sakai, [0036-0041]).
Claim(s) 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu (US 2011/0018099 A1) in view of Origuchi (US 2009/0237900 A1) as applied to claims 1 and 12 above and further in view of Shan (US 2017/0359898 A1).
Regarding Claim 10, Muramatsu in view of Origuchi teaches the limitations of the preceding claim.
Muramatsu does not disclose the electronic device of claim 1, wherein: the electronic component comprises a deep trench capacitor.
Shan (US 2017/0359898 A1) teaches of an electronic device (Fig 1-8), wherein: an electronic component (110; [0016]) comprises a deep trench capacitor ([0016]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Muramatsu in view of Origuchi, wherein: the electronic component comprises a deep trench capacitor as taught by Shan, in order to dampen power fluctuations (Shan, [0016]).
Regarding Claim 20, Muramatsu in view of Origuchi teaches the limitations of the preceding claim.
Muramatsu does not disclose the substrate of claim 12, wherein: the electronic component comprises a deep trench capacitor.
Shan (US 2017/0359898 A1) teaches of an electronic device (Fig 1-8), wherein: an electronic component (110; [0016]) comprises a deep trench capacitor ([0016]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate as taught by Muramatsu in view of Origuchi, wherein: the electronic component comprises a deep trench capacitor as taught by Shan, in order to dampen power fluctuations (Shan, [0016]).
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu (US 2011/0018099 A1) in view of Origuchi (US 2009/0237900 A1) as applied to claim 1 above and further in view of Masuda (US 2020/000599 A1).
Regarding Claim 11, Muramatsu in view of Origuchi teaches the limitations of the preceding claim and Muramatsu further references a computer ([0014]).
Muramatsu does not explicitly disclose the electronic device of claim 1, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle.
Masuda teaches of an electronic device ([0045]), wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone ([0045]), a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer ([0045]), a computer ([0045]), a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Muramatsu in view of Origuchi, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle as taught by Masuda, in order to provide an electronic device that can generate capacitance, improve capacitance per unit area and induce failure mode to be an open mode (Masuda, [0003-0008,0021,0045]). Furthermore an electronic device as taught by Muramatsu in view of Masuda would provide a means of electrical connection between different components and circuitry as part of a tablet computer or mobile phone, such as to provide electrical connections as party of the device’s functions.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
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