DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claims 20-31 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 11/24/2025.
Applicant's election with traverse of Group I in the reply filed on 11/24/2025 is acknowledged. The traversal is on the ground(s) that
The "product as claimed" in product claims cannot "be made by another materially different process." This is not found persuasive because the inventions are distinct, each from the other because the substrate can be made by another and materially different process (MPEP § 806.05(f)). In the instant case, instead of forming a cavity in the core and placing an embedded electrical device structure in the cavity of the core (a subtractive lithography process) the embedded electrical device structure could be placed on the core and the surrounding material build-up to from the core (an additive lithography process).
There is no undue or serious burden on the Office to search and examine claims 20-24 as containing features related in claims in Group I. Applicant argues that “it would not be burdensome to examine the device and method claims together. Although, the Inventions may appear similar their differences would require a different field of search (e.g., searching different classes /subclasses or electronic resources, or employing different search strategies or search queries). In finding art that may be readable on one invention it may not be applicable to another, or furthermore, to the species.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/03/2025, 01/02/2025, 11/14/2024 and 07/26/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-10, 12-13 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Inoue et al. (PG Pub 2009/0084596; hereinafter Inoue) and Verhaverbeke et al. (PG Pub 2022/0157740; hereinafter Verhaverbeke).
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Regarding claim 1, refer to Fig. 1 provided above, Inoue teaches a substrate 200, comprising:
a first metallization structure 209 comprising one or more first metallization layers (annotated “layers-1” in Fig. 1 above);
a second metallization structure 210 comprising one or more second metallization layers (annotated “layers-2” in Fig. 1 above); and
a core 201,204b,206 between the first metallization structure and the second metallization structure in a first direction (vertical direction), the core having a first height (annotated “h1” in Fig. 1 above) in the first direction, the core comprising:
a cavity 206a; and
an embedded electrical device structure 205 having a second height (annotated “h2” in Fig. 1 above) of at least the first height in the first direction (see Fig. 1), the embedded electrical device structure disposed in the cavity and comprising:
a first electrical device 205 adjacent to the first metallization structure and;
Although, Jeong teaches the core having a first height in the first direction, and the core is between the first metallization structure and the second metallization structure in the first direction, wherein the core comprises a cavity and an embedded electrical device structure, he does not explicitly teach wherein the embedded electrical device structure comprises a first electrical device and a second component adjacent to the first electrical device; wherein the embedded electrical device structure has a second height of at least the first height in the first direction.
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In the same field of endeavor, refer to the Examiner’s mark-up of a portion of Fig. 8I provided above, Verhaverbeke teaches a package structure 770 comprising: an embedded electrical device structure 630,844,626-top and 626-bottom) comprising a first electrical device (626-bottom) and a second component (626-top) adjacent to the first electrical device (see fig. 8i); wherein the embedded electrical device structure has a second height (height of 302+619; which is = to height 1) of at least the first height (302+619) in a first direction (vertical direction).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the embedded electrical device structure of Inoue with that of Verhaverbeke, to create a more robust package.
Regarding claim 2, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Verhaverbeke teaches the first electrical device (626-bottom) has a third height (height of that device) in the first direction less than the second height (h2) (see Fig. 8i).
Regarding claim 3, refer to the figures cited above, the combination of Inoue and Verhaverbeke teach the first electrical device (205-Inoue = 626-bottom of Verhaverbeke) comprises a first side (bottom side) adjacent to the first metallization structure 209 and a second side (top side) opposite the first side in the first direction (vertical direction; see Fig. 8i); and the second component (626-top of Verhaverbeke) comprises a third side (bottom side) adjacent to the second side of the first electrical device and a fourth side (top side) opposite the third side in the first direction (see Fig. 8i), the fourth side adjacent to the second metallization structure 210.
Regarding claim 4, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Inoue teaches the core 201,204b,206 comprises a first surface (bottom) adjacent to the first metallization structure 209 and a second surface (top) opposite the first surface in the first direction (vertical direction ; see Fig. 1), the second surface adjacent to the second metallization structure 210; the first side of the first electrical device is co-planar with the first surface of the core (see Fig. 1); and the fourth side of the second component (top side of 626 of Verhaverbeke) is co-planar with the second surface of the core (see Fig. 1).
Regarding claim 5, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Verhaverbeke teaches the first electrical device (626-bottom) is directly connected (through 848) to the second component (626-top) (see Fig. 8i).
Regarding claim 6, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Verhaverbeke teaches a film material 848 in the cavity 305 between the first electrical device (626-bottom) and the second component (626-top) (see Fig. 8i).
Regarding claim 7, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Verhaverbeke teaches an adhesive layer 848 in the cavity 305 between the first electrical device (626-bottom) and the second component (626-top) (see Fig. 8i).
Regarding claim 8, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Verhaverbeke teaches the second component (626-bottom) comprises a second electrical device (para [0065]).
Regarding claim 9, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Verhaverbeke teaches the second component (626-top) comprises a silicon spacer (para [0132]).
Regarding claim 10, refer to the figures cited above, the combination of Inoue and Verhaverbeke, teach the second component (626-top of Verhaverbeke) comprises a second electrical device (para [0065]); the first electrical device (205-Inoue = 626-bottom of Verhaverbeke) comprises: a first front side (bottom side) adjacent to the first metallization structure 209; a first back side (top side) opposite the first front side in the first direction (vertical direction); and one or more first metal interconnects (630,844-bottom side of Verhaverbeke) each exposed from the first front side and coupled to the first metallization structure (see combined figures); and the second electrical device (626-top) comprises: a second front side (bottom) adjacent to the first back side of the first electrical device (see Fig. 8i); a second back side opposite the second front side in the first direction, the second back side adjacent to the second metallization structure (see Fig. 8i); and one or more second metal interconnects 630,844 (top side) each exposed from the second front side (see Fig. 8i).
Regarding claim 12, refer to the figures cited above, the combination of Inoue and Verhaverbeke, teach the second component (626-top) comprises a second electrical device (para [0065]); the first electrical device (205-Inoue = 626-bottom of Verhaverbeke) comprises: a first front side (bottom side) adjacent to the first metallization structure 209; a first back side (top side) opposite the first front side in the first direction (vertical direction) (see Fig. 8i); and one or more first metal interconnects (630,844 on the bottom) each exposed from the first front side and coupled to the first metallization structure (see combined figures); and the second electrical device (626-top) comprises: a second back side (bottom side) adjacent to the first back side of the first electrical device (see Fig. 8i); a second front side (top side) opposite the second back side in the first direction (vertical direction), the second front side adjacent to the second metallization structure 210 (see combined figures); and one or more second metal interconnects (630,844 on the top) each exposed from the second front side and coupled to the second metallization structure 210.
Regarding claim 13, refer to the figures cited above, the combination of Inoue and Verhaverbeke, teach an adhesive layer 848 in the cavity 305 between the first electrical device (626-bottom) and the second electrical device (626-top) (see Fig. 8i).
Regarding claim 17, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Inoue teaches the embedded electrical device structure 205 is at least partially embedded in the cavity 206a (see fig. 8i).
Regarding claim 18, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Inoue teaches the first electrical device is a device comprised from the group consisting of a passive device (para [0008] and [0077]), capacitor, a deep trench capacitor (DTC), a resistor, an inductor, an integrated circuit (IC), and an IC die.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Inoue and Verhaverbeke, as applied to claim 10 above, and further in view of Vaidya et al. (PG Pub 2021/0272881; hereinafter Vaidya).
Regarding claim 11, refer to the figures cited above, in the combination of Inoue and Verhaverbeke, Verhaverbeke teaches at least one second metal interconnect 630,844 of the one or more second metal interconnects is coupled to at least one via of the one or more vias (see Fig. 8i). They do not teach the one or more vias each coupled to the first metallization structure and extending through the first electrical device from the first front side to the first back side in the first direction.
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In the same field of endeavor, refer to Fig. 9a-provided above, Vaidya teaches a semiconductor device 900a comprising: one or more vias 102 each coupled to a first metallization structure 905 and extending through a first electrical device 500 from the first front side (bottom) to the first back side (top) in the first direction (vertical direction).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the one or more vias extending through the first electrical device, as taught by Vaidya, to provide electrical communication between the first and second electrical device/component.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Inoue and Verhaverbeke, as applied to claim 1 above, and further in view of Watanabe (PG Pub 2017/0345767; hereinafter Watanabe).
Regarding claim 19, refer to the figures cited above, the combination of Inoue and Verhaverbeke, teach the wiring substrate of claim 1 (se claim 1), they do not explicitly teach the wiring substrate is integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.
In the same field of endeavor, Watanabe teaches a multilayer wiring substrate is integrated into at least a television (para [0058-0059]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the wiring substrate of Inoue and Verhaverbeke into a television, as taught by Matanabe, to create a moving picture.
Allowable Subject Matter
Claims 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 14 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 14, the second component comprises a spacer structure; the first electrical device comprises: a first front side adjacent to the first metallization structure; a first back side opposite the first front side in the first direction; and one or more first metal interconnects each exposed from the first front side and coupled to the first metallization structure; and the spacer structure comprises: a second front side adjacent to the first back side of the first electrical device; a second back side opposite the second back side in the first direction, the second front side adjacent to the second metallization structure. Claims 15-16 would be allowable, because they depend on allowable claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817