DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 01/26/2026 has been entered. Applicant's amendment has overcome
the Claims 112 (b) rejections previously set forth in the Non-Final Office Action dated on 10/17/2025. Claims 2-4, 10-11,19-22 and 24 are canceled by Applicant. Claims 1,5-9, 12-18,23 and 25-30 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 01/26/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with references of the record, JP 2007067369 A to Yamamoto and US 20240222213 A1 to Boja, being used in the current rejection, see detail below.
Election/Restrictions
Applicant’s amendment of claims 9 and 23 with its dependent claims 12-13 and 25, respectively, directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: claim 9 has limitations of "a second cured resin layer filling disposed in a third region of the cavity between the first region of the cavity and the second region of the cavity, the second cured resin layer extending between the plurality of exterior sidewalls of the electronic component and the plurality of interior sidewalls of the core, and wherein the first cured resin layer and the second cured resin layer are formed from different resin materials”. Claim 23 has limitations of “a second cured resin layer filling disposed in a third region of the cavity between the first region of the cavity and the second region of the cavity, the second cured resin layer extending between the plurality of exterior sidewalls of the electronic component and the plurality of interior sidewalls of the core, and wherein the first cured resin layer and the second cured resin layer are formed from different resin materials”. These limitations in claims 9 and 23 describe another Species (Fig. 6B) that it is different to Species disclosed in claim 1 (Fig. 4B), then, brings restriction by Species.
The requirement is deemed proper, and is therefore made FINAL. Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 9,12-13,23 and 25 withdrawn from consideration as being directed to non-elected Species and become an election without traverse. See 37 CFR 1.142(b) and MPEP § 821.03.
In view of the above, this office action considers:
Claims 1,5-9, 12-18,23 and 25-30 are pending.
Claims 9,12-13,23 and 25 are withdrawn, non-elected without traverse.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-8, 14-15 and 17-18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (JP 2007067369 A, hereinafter Yamamoto, of the record) in view of Boja (US 20240222213 A1, hereinafter Boja, of the record).
Re: Independent Claim 1, Yamamoto teaches an electronic device (Fig. 1), comprising:
a substrate (10 a wiring board in [0036], Fig. 1) comprising:
a core (11 a substrate core in [0036], Fig. 1) having an upper planar surface and a lower planar surface (Fig. 1), wherein
the core (11) includes a cavity (cavity a region including the component 101 in [0036], Fig. 1-Annotated) extending between the upper planar surface of the core (11) and the lower planar surface of the core (11), and wherein the cavity (cavity) is defined by a plurality of interior sidewalls of the core (11);
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Yamamoto’s Figure 1-Annotated.
an electronic component (101 a ceramic capacitor in [0037], Fig. 1) at least partially disposed (Fig. 1) in the cavity (cavity), wherein the electronic component (101) comprises an upper planar surface having one or more electronic component terminals (116 metallized layers in [0044], Fig. 1), the electronic component (101) further comprising a plurality of exterior sidewalls facing (Fig. 1) the plurality of interior sidewalls of the core (11);
a first cured resin layer (first resin-92a a resin filler in [0055], Fig. 1-Annotated), wherein the first cured resin layer (first resin-92a) extends over the upper planar surface of the electronic component (101) and about the electronic component terminals (116), wherein the first cured resin layer (first resin-92a) is further disposed in a first region (Fig. 1-Annotated) of the cavity (cavity) between the plurality of exterior sidewalls of the electronic component (101) and the plurality of interior sidewalls of the core (11);
a dielectric fill material (33-f a resin insulating layer filling into the cavity in [0041], Fig. 1-Annotated) disposed in a second region (Fig. 1-Annotated) of the cavity (cavity); and
an upper metallization structure disposed (32 a build-up layer including 34,36,38 in [0057], Fig. 1) over the upper planar surface of the core (11), wherein the upper metallization structure (32) is configured to provide one or more conductive paths (Fig. 1-Annotated) from the one or more electronic component terminals (116) to one or more upper metal terminals of the upper metallization structure (32), the upper metallization structure (32) including a lower dielectric layer (34 insulating layer in [0038], Fig. 1), wherein the first cured resin layer (first resin-92a) is further disposed in a region of the cavity (cavity) between (Fig. 1-Annotated) the upper planar surface of the electronic component (101) and a lower surface of the lower dielectric layer (34).
Yamamoto does not expressly disclose a dielectric fill material disposed in a second region of the cavity between the plurality of exterior sidewalls of the electronic component and the plurality of interior sidewalls of the core.
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Boja’s Figure 1A-Annotated.
However, in the same semiconductor device field of endeavor, Boja discloses a dielectric fill material (116c a portion of the first insulation layer 116a in [0035], Fig. 1A) disposed in a second region of the cavity (cavity a region including the component 115a in [0022], Fig. 1A) between (Fig. 1A-Annotated) the plurality of exterior sidewalls of the electronic component (115a active device component in [0022], Fig. 1A) and the plurality of interior sidewalls of the core (102a a monolithic core in [0049], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Boja’s feature of a dielectric fill material disposed in a second region of the cavity between the plurality of exterior sidewalls of the electronic component and the plurality of interior sidewalls of the core to Yamamoto’s device to facilitate heat dissipation from device components and/or shorten or simply the routing to chiplets and/or further alter the device component's electrical properties ([0020], Boja).
Re: Claim 5, Yamamoto modified by Boja discloses the electronic device of claim 1,
Yamamoto does not expressly disclose wherein: the electronic component has a height that is greater than or equal to a depth of the core.
However, in the same semiconductor device field of endeavor, Boja discloses a wherein: the electronic component (115a active device component in [0022], Fig. 1A) has a height that is greater than or equal (Fig. 1A) to a depth of the core (102a a monolithic core in [0049], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Boja’s feature wherein: the electronic component has a height that is greater than or equal to a depth of the core to Yamamoto’s device to facilitate heat dissipation from device components and/or shorten or simply the routing to chiplets and/or further alter the device component's electrical properties ([0020], Boja).
Re: Claim 6, Yamamoto modified by Boja discloses the electronic device of claim 5, wherein: the core (11, Yamamoto) has a thickness equal to or less than 760 micrometers (a thickness less than of 1mm in [0049], Fig. 1, Yamamoto).
Re: Claim 7, Yamamoto modified by Boja discloses the electronic device of claim 1, further comprising: a lower metallization structure (31 a build-up layer including 33,35,37 in [0041], Fig. 1, Yamamoto) disposed below the lower planar surface of the core (11 Yamamoto), wherein the lower metallization structure (31 Yamamoto) is configured to provide one or more conductive paths from a patterned metallization layer (42 conductor layers in [0037], Fig. 1 Yamamoto) disposed over the lower planar surface of the core to one or more lower metal terminals of the lower metallization structure (31 Yamamoto), the lower metallization structure (31 Yamamoto) comprising an upper dielectric layer (33 an insulating layer in [0041], Fig. 1, Yamamoto) disposed over and adjacent the lower planar surface of the core (11, Yamamoto).
Re: Claim 8, Yamamoto modified by Boja discloses the electronic device of claim 7, wherein: the dielectric fill material (33f Yamamoto) comprises a same dielectric material (33-f made of the same material of 33, Fig. 1-Annotated) as the upper dielectric layer (33 an insulating layer in [0041], Fig. 1, Yamamoto) of the lower metallization structure (31 Yamamoto).
Re: Claim 14, Yamamoto modified by Boja discloses the electronic device of claim 1, further comprising: one or more metal vias (16 through-hole conductors in [0036], Fig. 1, Yamamoto) extending between (Fig. 1, Yamamoto) the upper planar surface of the core (11, Yamamoto) and the lower planar surface of the core (11, Yamamoto).
Re: Claim 15, Yamamoto modified by Boja discloses the electronic device of claim 1, further comprising: an electronic circuit package (motherboard, a plurality of solder bumps 49 are arranged on the surface of the BGA pad 48 for electrical connection to a motherboard in [0038], Fig.1, Yamamoto) mounted at the one or more upper metal terminals of the upper metallization structure (32, Yamamoto).
Re: Claim 17, Yamamoto modified by Boja discloses the electronic device of claim 1, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle (a computer in [0002] , Yamamoto).
Re: Independent Claim 18, Yamamoto teaches a substrate (Fig. 1), comprising:
a substrate (10 a wiring board in [0036], Fig. 1) comprising:
a core (11 a substrate core in [0036], Fig. 1) having an upper planar surface and a lower planar surface (Fig. 1), wherein the core (11) includes a cavity (cavity a region including the component 101 in [0036], Fig. 1-Annotated) extending between the upper planar surface of the core (11) and the lower planar surface of the core (11), and wherein the cavity (cavity) is defined by a plurality of interior sidewalls of the core (11);
an electronic component (101 a ceramic capacitor in [0037], Fig. 1) at least partially disposed (Fig. 1) in the cavity (cavity), wherein the electronic component (101) comprises an upper planar surface having one or more electronic component terminals (116 metallized layers in [0044], Fig. 1), the electronic component (101) further comprising a plurality of exterior sidewalls facing (Fig. 1) the plurality of interior sidewalls of the core (11);
a first cured resin layer (first resin-92a a resin filler in [0055], Fig. 1-Annotated), wherein the first cured resin layer (first resin-92a) extends over the upper planar surface of the electronic component (101) and about the electronic component terminals (116), wherein the first cured resin layer (first resin-92a) is further disposed in a first region (Fig. 1-Annotated) of the cavity (cavity) between the plurality of exterior sidewalls of the electronic component (101) and the plurality of interior sidewalls of the core (11);
a dielectric fill material (33-f a resin insulating layer filling into the cavity in [0041], Fig. 1-Annotated) disposed in a second region (Fig. 1-Annotated) of the cavity (cavity); and
an upper metallization structure disposed (32 a build-up layer including 34,36,38 in [0057], Fig. 1) over the upper planar surface of the core (11), wherein the upper metallization structure (32) is configured to provide one or more conductive paths (Fig. 1-Annotated) from the one or more electronic component terminals (116) to one or more upper metal terminals of the upper metallization structure (32) ), the upper metallization structure (32) including a lower dielectric layer (34 insulating layer in [0038], Fig. 1), wherein the first cured resin layer (first resin-92a) is further disposed in a region of the cavity (cavity) between (Fig. 1-Annotated) the upper planar surface of the electronic component (101) and a lower surface of the lower dielectric layer (34).
Yamamoto does not expressly disclose a dielectric fill material disposed in a second region of the cavity between the plurality of exterior sidewalls of the electronic component and the plurality of interior sidewalls of the core.
However, in the same semiconductor device field of endeavor, Boja discloses a dielectric fill material (116c a portion of the first insulation layer 116a in [0035], Fig. 1A) disposed in a second region of the cavity (cavity a region including the component 115a in [0022], Fig. 1A) between (Fig. 1A-Annotated) the plurality of exterior sidewalls of the electronic component (115a active device component in [0022], Fig. 1A) and the plurality of interior sidewalls of the core (102a a monolithic core in [0049], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Boja’s feature of a dielectric fill material disposed in a second region of the cavity between the plurality of exterior sidewalls of the electronic component and the plurality of interior sidewalls of the core to Yamamoto’s device to facilitate heat dissipation from device components and/or shorten or simply the routing to chiplets and/or further alter the device component's electrical properties ([0020], Boja).
Claim(s) 16 and 26 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Boja and further in view of Hsieh (US 20210159187 A1, hereinafter Hsieh, of the record).
Re: Claim 16, Yamamoto discloses the electronic device of claim 1,
Yamamoto does not expressly disclose wherein: the electronic component comprises a deep trench capacitor.
However, in the same semiconductor device field of endeavor, Hsieh discloses a wherein: the electronic component comprises a deep trench capacitor (30 a deep trench capacitor in [0029], Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsieh’s feature wherein: the electronic component comprises a deep trench capacitor to Yamamoto’s device to provides a more efficient use of space for the semiconductor device ([0026], Hsieh).
Re: Claim 26, Yamamoto discloses the substrate of claim 18,
Yamamoto does not expressly disclose wherein: the electronic component comprises a deep trench capacitor.
However, in the same semiconductor device field of endeavor, Hsieh discloses a wherein: the electronic component comprises a deep trench capacitor (30 a deep trench capacitor in [0029], Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsieh’s feature wherein: the electronic component comprises a deep trench capacitor to Yamamoto’s device to provides a more efficient use of space for the semiconductor device ([0026], Hsieh).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim et al. (US 20150049445 A1) teaches “METHOD FOR MANUFACTURING ELECTRONIC COMPONENT EMBEDDING SUBSTRATE AND ELECTRONIC COMPONENT EMBEDDING SUBSTRATE”. This document is related to an electronic component embedding substrate and an electronic component embedding substrate.
Kiwanami et al. (US 20140360760 A1) teaches “WIRING SUBSTRATE AND MANUFACTURING METHOD OF WIRING SUBSTRATE”. This document is related to a wiring substrate includes a core, a first wiring layer formed on a first surface of the core, a second wiring layer formed on a second surface of the core, and an electronic component partially accommodated in the cavity and including a projected portion projected from the first opening of the core.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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