DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Castro et al. (US 2020/0066343 A1), and further in view of Fugazza et al. (US 2022/0113892 A1).
Regarding claim 1, Castro teaches a device, comprising: a memory cell (Fig. 1);
at least one voltage driver operable to apply voltage pulses in a first polarity and a second polarity (Fig. 1 inherently have a drivers connected to the word line WL and the bit lines, which applies voltages in a first and second polarity, see Fig. 4); and
a circuit configured to control the at least one voltage driver to drive voltage pulses according to more than two polarity patterns to respectively store more than two values in the memory cell (Fig. 4, show more than two polarity patterns for storing data in the memory cells. Castro teaches the memory cell can be multi-level memory cells which store more than one bit of data. E.g. two bits will produce 4 values, see ¶0019).
wherein a first voltage pulse driven to a wordline of the memory cell has a different polarity to a simultaneous second voltage pulse driven to a bitline of the memory cell (Fig. 1, memory cells are located between wordline WL_T and a bit line DL. In Fig. 4, Castro teaches applying a first voltage 425 to the wordline of the memory cell and has a different polarity simultaneous second voltage 430 applied to the bit line of the memory cell).
Castro did not explicitly explain how the memory cell will be programmed to store more than two values in the memory cell. A person with the ordinary skills in the art would be able to understand changing the voltages in a single bit memory cell as shown in Fig. 4 would produce different threshold voltages in the memory cell to produce more than two values in the memory cell. In order to expedite the prosecution of this case, Fugazza is used to teach this limitation.
Fugazza teaches phase change memory cell (¶0062) can store more than two values (Fig. 5, Fig. 6 or Fig. 11), the memory cell can be programmed to desired state may be accomplished by changing polarity, magnitude and the duration of the applied program pulse (¶0076 to ¶0078). In addition, Fugazza teaches wherein a first voltage pulse driven to a wordline of the memory cell has a different polarity to a simultaneous second voltage pulse driven to a bitline of the memory cell (Fugazza teaches memory cell connected between word lines 215 and column lines 217. Fugazza teaches the program pulse can be applied using a first voltage having a positive polarity to the first line and applying a second voltage having a second polarity simultaneously to the second line, see ¶0078).
It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to modify the polarity, magnitude and duration for the memory program pulse in order to change the threshold voltage for the memory cell which will result in having the memory cell store multiple program state (Fig. 11, shows memory cell stores 8 values).
Regarding claim 2, Castro teaches the device of claim 1, wherein to store a first value among the more than two values, a first pattern among the more than two polarity patterns is configured to drive a voltage pulse across the memory cell to cause at least a predetermined current to go through the memory cell in a first direction (Fig. 4, Timing diagram 405 or 410).
Regarding claim 3, Castro teaches the device of claim 2, wherein to store a second value among the more than two values, a second pattern among the more than two polarity patterns is configured to drive a voltage pulse across the memory cell to cause at least the predetermined current to go through the memory in a second direction different from the first direction (Fig. 4, Timing diagram 415 or 420).
Regarding claim 4, Castor teaches the device of claim 3, wherein to store a third value among the more than two values, a third pattern among the more than two polarity patterns is configured to: drive a first voltage pulse across the memory cell to cause at least the predetermined current to go through the memory cell in a first direction; and drive a second voltage pulse, different from the first voltage pulse, across the memory cell (Fig. 4, Timing diagram 420).
Regarding claim 5, Castor teaches the device of claim 4, wherein the first voltage pulse is in the first polarity and the second voltage pulse is in the second polarity (Fig. 4, first voltage 445-a and the second pulse 450 is in the second polarity).
Regarding claim 6, Fugazza the device of claim 5, wherein changing the width of the duration can result in producing different threshold voltages for the memory cell, which will result in producing different values to be stored in the memory cell. Fugazza does not explicitly teach the second voltage pulse is no more than one tenth of a duration of the first voltage pulse. However, it would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to try different width pulse such as to use a second voltage pulse is no more than one tenth of a duration of the first voltage pulse in order to have different memory threshold voltages.
Regarding claim 7, Castro teaches the device of claim 4, wherein the memory cell is connected between a first line and a second line; wherein the first voltage pulse includes a positive voltage of a magnitude applied to the first and a negative voltage of the magnitude applied to the second line; and wherein the second voltage pulse includes the positive voltage of the magnitude applied to the first line and the negative voltage of a reduced magnitude applied to the second line (¶0063).
Regarding claim 8, Castro teaches the device of claim 7, wherein the reduced magnitude is substantially reduced to zero (The reduced magnitude for the negative voltage is reduced to substantially zero).
Regarding claim 9, Castro teaches the device of claim 4, wherein the first voltage pulse is in the first polarity and of a first magnitude; and wherein the second voltage pulse is in the first polarity and of a half of the first magnitude (Fig. 4).
Regarding claim 10, Castro teaches the device of claim 4, wherein the second voltage pulse is insufficient to place the memory cell in a conductive state (¶0066).
Regarding claims 11-20, the claims have similar limitations as claims 1-10. Therefore, the claims are rejected under the same grounds of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 11-13 and 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fugazza et al. (US 2022/0113892 A1).
Regarding claim 1, Fugazza teaches a device, comprising:
a memory cell (Fig. 2, 207);
at least one voltage driver operable to apply voltage pulses in a first polarity and a second polarity; and a circuit configured to control the at least one voltage driver to drive voltage pulses according to more than two polarity patterns to respectively store more than two values in the memory cell thereby storing more than one bit of data in the memory cell (In Fig. 5, Fig. 6, Fig. 11, Fugazza teaches an inherent voltage driver that applies voltage pulses during the write operation to the memory cell. The control circuit will apply voltage pulses in a first polarity and second polarity. Fugazza teaches different polarity patterns by using different magnitude, different polarity and different duration width in order to store more than two values in the memory cell by storing more than one bit of data in the memory cell), wherein a first voltage pulse driven to a wordline of the memory cell has a different polarity to a simultaneous second voltage pulse driven to a bitline of the memory cell (Fugazza teaches memory cell connected between word lines 215 and column lines 217. Fugazza teaches the program pulse can be applied using a first voltage having a positive polarity to the first line and applying a second voltage having a second polarity simultaneously to the second line, see ¶0078).
Regarding claim 2, Fugazza further teaches the device of claim 1, wherein to store a first value among the more than two values, a first pattern among the more than two polarity patterns is configured to drive a voltage pulse across the memory cell to cause at least a predetermined current to go through the memory cell in a first direction (Fig. 5, Fig. 6 storing fist value e.g. storing 11 or in Fig. 11 storing a first value e.g. 111).
Regarding claim 3, Fugazza further teaches the device of claim 2, wherein to store a second value among the more than two values, a second pattern among the more than two polarity patterns is configured to drive a voltage pulse across the memory cell to cause at least the predetermined current to go through the memory in a second direction different from the first direction (Fig. 5, Fig. 6 storing fist value e.g. storing 00 or in Fig. 11 storing a first value e.g. 000).
Regarding claims 11-13 and 19-20, the claims have similar limitations as claims 1-3. Therefore, the claims are rejected under the same grounds of rejection.
Response to Arguments
Applicant's arguments filed on 1/22/2026 have been fully considered but they are not persuasive.
Applicant’s representative argues on page 2 “In contrast, Fugazza, the newly added reference used in the Office Action as allegedly teaching a memory cell that can store more than one bit of data, does not teach or suggest such wordline and bitline voltages that have different polarities. For example, Fig. 6 of Fugazza below shows different pulses 602 that may be used to write into a memory. Fig. 6 of Fugazza also shows curves 612 and 614 that may have different polarities, but the curves 612 and 614 do not relate to simultaneous voltages that are applied to word and bit lines to program a multi-level memory cell…”
Fugazza teaches a memory cell connected between word lines 215 and column lines 217. Fugazza teaches the program pulse can be positive or negative pulses to program the memory cell to one of the states. Fugazza teaches the program pulse can be applied using a first voltage having a positive polarity to the first line and applying a second voltage having a second polarity simultaneously to the second line, see ¶0078.
Applicant’s argues on page 3 “Fig. 4 of Castro shows programming of a cell with different word and bit line voltages, but, as discussed in prior correspondence, Castro does not teach or suggest programming cells with more than one bit of data as claimed.”
Memory cells will store data based on the electrical resistance or the threshold voltage of the memory cell, ¶0024. The resistance for the memory cell can be changed based on the voltage applied across the memory cell. Castro teaches applying a first voltage applying a first voltage 425 to the wordline of the memory cell and has a different polarity simultaneous second voltage 430 applied to the bit line of the memory cell, see Fig. 4. Castro only described the program operation for one bit memory cell. However, Castro teaches the memory cells can program multiple bits in the memory cell. It is obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to program different levels of resistance into the memory cell to produce multiple bits by changing the magnitude of the program voltages, which can be supported by Fugazza (¶0076). Therefore, modifying the magnitude and polarity of the program pulses in Castro invention will produce multiple bits stored in the memory cell.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824