Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-23 are rejected under 35 U.S.C. 103 as obvious over Miyazaki et al. (Pub. No.: US 2014/0374793 A1).
Regarding Claim 1, Miyazaki et al. discloses a semiconductor device, comprising: a semiconductor body having a first surface and a second surface (Par. 0056-0062; Figs. 1-21), the semiconductor body comprising: a depletion region further comprising a width of the depletion region that is WD (Par. 0056-0062 & 0082-0083; Figs. 1-21 – depletion region extending mainly at least into a part of the drift layer 1 extending from the pn junction formed between p base layer 2 and n- drift layer 1), a drift region having a first conductivity type (Par. 0056-0062; Figs. 1-21 – drift layer 1 of n-type conductivity),
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an island region having a first conductivity type (Par. 0056-0062; Figs. 1-21 – island region 10a of n-type conductivity), a buffer region having a first conductivity type (Par. 0056-0062; Figs. 1-21 – buffer region 10b of n-type conductivity), wherein the drift region is more proximal to the first surface of the semiconductor body than the buffer region (Figs. 1-21), wherein the depletion region is located within the drift region (Par. 0056-0062; Figs. 1-21), and wherein the island region is located within the drift region, and an ion concentration of the first conductivity type of the island region is higher than an ion concentration of the first conductivity type of the drift region (Figs. 1-21). Miyazaki et al. does not explicitly disclose the semiconductor device, wherein the island region has a top surface with a position thereof that is in a range of 65%WD to 80% WD, a position of a bottom surface of the island region is at WD, and a thickness of the island region is in a range of 20%WD to 35% WD.
However, this prior at teaches that the width of the depletion layer reaches the end of the first field stop layer 10a when the device is turned off (Par.0095). So, the depletion width on the n-side is the sum of the thickness of the drift region 1 between the first field stop layer 10a and the p base layer 2 and the thickness of the first field stop layer. Now, how thick the first field stop layer 10a would be compared to the thickness of the aforementioned drift region 1 depends on quite a few factors including the reverse bias voltage, the doping concentration and the thickness of both the drift layer and the field stop layer etc. To expand on this, the ratio between the width of the first field stop layer and the total width of the depletion layer is well-known to be a result-effective variable. If the ratio is too high, the switching speed could be too slow and there would be more losses. If the ratio is too low, on the other hand, the recovery could be snappy and there could be potentially dangerous voltage spike and oscillation. The optimized ratio would depend on the field of application of the device, i.e., the rated voltage, the speed required, the stray inductance, the desired softness etc. Miyazaki et al. discloses the claimed invention except for the semiconductor device, wherein a position of a top surface of the island region is in a range of 65%WD to 80% WD, a position of a bottom surface of the island region is at WD, and a thickness of the island region is in a range of 20%WD to 35% WD. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to adapt the semiconductor device, wherein
a position of a top surface of the island region is in a range of 65%WD to 80% WD, a position of a bottom surface of the island region is at WD, and a thickness of the island region is in a range of 20%WD to 35% WD, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 2, Miyazaki et al., as applied to claim 1, discloses the semiconductor device, further comprising a Poisson's equation in the drift region that is calculated as:
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wherein Q(x) is a charge within the depletion region, Es is a dielectric constant for the semiconductor, q is an electron charge, and ND is an ion impurity concentration in the drift region (Par. 0056-0062; Figs. 1-21 – implied).
Regarding Claim 3, Miyazaki et al., as applied to claim 2, discloses the semiconductor device, wherein the semiconductor body further comprises: a semiconductor region of a second conductivity type, and an ion concentration of the semiconductor region of the second conductivity type that is higher than an ion concentration of the drift region so that the depletion region extends only towards the drift region to maintain a blocking voltage in response to applying a reverse voltage to the semiconductor device (Par. 0056-0062; Figs. 1-21 – semiconductor region 2 (p base region)).
Regarding Claim 4, Miyazaki et al., as applied to claim 2, discloses the semiconductor device, further comprising an electric field value that becomes zero at X=WD, and an electric field distribution equation is:
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wherein the electric field distribution equation is obtained by using a boundary condition with the potential being zero at x=0 within the semiconductor region of the second conductivity type (Par. 0056-0062; Figs. 1-21 – implied).
Regarding Claim 5, Miyazaki et al., as applied to claim 4, discloses the semiconductor device, wherein the voltage at the width of the depletion region WD is equal to an applied reverse bias Va:
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wherein the width of the depletion region WD is given by:
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(Par. 0056-0062, 0095; Figs. 1-21 – implied; this prior at teaches that the width of the depletion layer reaches the end of the first field stop layer 10a when the device is turned off; so the depletion width on the n-side is the sum of the thickness of the drift region 1 between the first field stop layer 10a and the p base layer 2 and the thickness of the first field stop layer; how thick the first field stop layer 10a would be compared to the thickness of the aforementioned drift region 1 depends on quite a few factors including the reverse bias voltage, the doping concentration and the thickness of both the drift layer and the field stop layer).
Regarding Claim 6, Miyazaki et al. et al., as applied to claim 1, discloses the semiconductor device, wherein the semiconductor body further comprises: a semiconductor region of a second conductivity type, and an ion concentration of the semiconductor region of a second conductivity type that is close to the ion concentration of the drift region so that the depletion region extends towards the semiconductor region of the second conductivity type and the drift region to maintain a blocking voltage in response to applying a reverse voltage to the semiconductor device (Par. 0056-0062; Fig. 2 – semiconductor region 2 of p type conductivity; now ‘close’ is a relative term; under BRI, it can be said that the ion concentration of the semiconductor region of a second conductivity type is close to the ion concentration of at least some part of the drift region, either 1 or 10a).
Regarding Claim 7, Miyazaki et al., as applied to claim 6, discloses the semiconductor device, further comprising a width of the depletion region WD that is calculated as:
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wherein
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is a dielectric constant for the semiconductor, q is an electron charge, ND is an ion impurity concentration in the drift region, NA is an ion impurity concentration in the semiconductor region of the second conductivity type, and Va is a reverse bias applied to the semiconductor (Par. 0056-0062, 0095; Figs. 1-21 – implied).
Regarding Claim 8, Miyazaki et al. et al., as applied to claim 1, discloses the semiconductor device, wherein the first conductivity type of the buffer region has an ion concentration that is higher than an ion concentration of the first conductivity type of the drift region (Fig. 1).
Regarding Claim 9, Miyazaki et al., as applied to claim 5, discloses the semiconductor device, wherein the top surface of the island region is more proximal to the first surface of the semiconductor than the bottom surface of the island region (Par. 0056-0062; Fig. 1).
Regarding Claim 10, Miyazaki et al., as applied to claim 1, discloses the semiconductor device, wherein the island region is doped by single peak doping or multi peak doping, and the shape of an ion doping profile of the island region comprises at least one peak selected from the group consisting of: a triangle single peak, a quadrangle single peak, and irregular multi peaks (Fig. 1).
Regarding Claim 11, Miyazaki et al., as applied to claim 1, discloses the semiconductor device, wherein the semiconductor device comprises at least one device selected from the group consisting of: a fast recovery diode, an ultra-fast recovery diode, a standard diode, a MOSFET, and an IGBT switch device (Par. 0056-0062; Fig. 2).
Regarding Claim 12, Miyazaki et al. discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a drift region of a first conductivity type on a semiconductor body (Par. 0056-0062; Figs. 1-21 – drift region comprising layer 1 of n-type conductivity), forming a semiconductor region of a second conductivity type on a first surface of the semiconductor body (Par. 0056-0062; Figs. 1-21 – semiconductor region 2 (p base region)), forming a semiconductor region of a first conductivity type on a second surface of the semiconductor body (Par. 0056-0062; Fig. 2 – semiconductor region of first conductivity type 10b), forming an island region of the first conductivity type and a buffer region of the first conductivity type on the semiconductor body (Par. 0056-0062; Figs. 1-21 – island region 10a of n-type conductivity; buffer region 10b of n-type conductivity), wherein the drift region is more proximal to the first surface of the semiconductor body than the buffer region (Fig. 1), and
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wherein within the drift region there is located a depletion region, and the depletion region comprises a width that is WD, wherein the island region is located within the drift region, and an ion concentration of the first conductivity type of the island region is higher than an ion concentration of the first conductivity type of the drift region (Par. 0056-0062; Fig. 2 – depletion region extending mainly at least into a part of the drift layer 1 extending from the pn junction formed between p base layer 2 and n- drift layer 1).
Miyazaki et al. does not explicitly disclose the semiconductor device, wherein the island region has a top surface with a position thereof that is in a range of 65%WD to 80% WD, a position of a bottom surface of the island region is at WD, and a thickness of the island region is in a range of 20%WD to 35% WD.
However, this prior at teaches that the width of the depletion layer reaches the end of the first field stop layer 10a when the device is turned off (Par.0095). So, the depletion width on the n-side is the sum of the thickness of the drift region 1 between the first field stop layer 10a and the p base layer 2 and the thickness of the first field stop layer. Now, how thick the first field stop layer 10a would be compared to the thickness of the aforementioned drift region 1 depends on quite a few factors including the reverse bias voltage, the doping concentration and the thickness of both the drift layer and the field stop layer etc. To expand on this, the ratio between the width of the first field stop layer and the total width of the depletion layer is a result-effective variable. If the ratio is too high, the switching speed would be too slow and there would be more losses. If the ratio is too low, on the other hand, the recovery could be snappy and there could be potentially dangerous voltage spike and oscillation. The optimized ratio would depend on the field of application of the device, i.e., the rated voltage, the speed required, the stray inductance etc. Miyazaki et al. discloses the claimed invention except for the semiconductor device, wherein a position of a top surface of the island region is in a range of 65%WD to 80% WD, a position of a bottom surface of the island region is at WD, and a thickness of the island region is in a range of 20%WD to 35% WD. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to adapt the semiconductor device, wherein
a position of a top surface of the island region is in a range of 65%WD to 80% WD, a position of a bottom surface of the island region is at WD, and a thickness of the island region is in a range of 20%WD to 35% WD, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 13, Miyazaki et al., as applied to claim 12, discloses the method, further comprising a Poisson's equation in the drift region that is calculated as below:
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wherein Q(x) is a charge within the depletion region, Es is a dielectric constant for the semiconductor, q is an electron charge, and ND is an ion impurity concentration in the drift region (Par. 0056-0062; Figs. 1-21 – implied).
Regarding Claim 14, Miyazaki et al., as applied to claim 13, discloses the method, wherein the semiconductor region of a second conductivity type has an ion concentration that is higher than an ion concentration of the drift region so that the depletion region extends only towards the drift region to maintain a blocking voltage in response to applying a reverse voltage to the semiconductor device (Par. 0056-0062; Fig. 1).
Regarding Claim 15, Friedrichs et al., as applied to claim 13, discloses the method, further comprising an electric field value that becomes zero at X=WD, and an electric field distribution equation is:
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wherein the equation is obtained by using a boundary condition with the potential being zero at x=0 within the semiconductor region of the second conductivity type (Par. 0056-0062; Fig. 1 – implied).
Regarding Claim 16, Miyazaki et al., as applied to claim 13, discloses the method, wherein the voltage at the width of the depletion region WD is equal to the applied reverse bias Va: wherein the width of the depletion region WD is given by:
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(Par. 0056-0062, 0095; Figs. 1-21 – implied; this prior at teaches that the width of the depletion layer reaches the end of the first field stop layer 10a when the device is turned off; so the depletion width on the n-side is the sum of the thickness of the drift region 1 between the first field stop layer 10a and the p base layer 2 and the thickness of the first field stop layer; how thick the first field stop layer 10a would be compared to the thickness of the aforementioned drift region 1 depends on quite a few factors including the reverse bias voltage, the doping concentration and the thickness of both the drift layer and the field stop layer).
Regarding Claim 17, Miyazaki et al., as applied to claim 12, discloses the method, wherein the semiconductor region of a second conductivity type has an ion concentration that is close to an ion concentration of the drift region so that the depletion region extends towards the semiconductor region of the second conductivity type and the drift region to maintain a blocking voltage in response to applying a reverse voltage to the semiconductor device (Par. 0056-0062; Fig. 1 – semiconductor region 2 of p type conductivity; now ‘close’ is a relative term; under BRI, it can be said that the ion concentration of the semiconductor region of a second conductivity type is close to the ion concentration of at least some part of the drift region, either 1 or 10a).
Regarding Claim 18, Miyazaki et al., as applied to claim 17, discloses the method, wherein the width of the depletion region WD that is calculated as:
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wherein
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is a dielectric constant for the semiconductor, q is an electron charge, ND is an ion impurity concentration in the drift region, NA is the ion impurity concentration in the semiconductor region of the second conductivity type, and Va is a reverse bias applied to the semiconductor (Par. 0056-0062, 0095; Figs. 1-21 – implied).
Regarding Claim 19, Miyazaki et al. et al., as applied to claim 12, discloses the method, wherein the first conductivity type of the buffer region has an ion concentration that is higher than the ion concentration of the first conductivity type of the drift region (Fig. 1).
Regarding Claim 20, Miyazaki et al. et al., as applied to claim 12, discloses the method, wherein the island region is formed by a proton implantation process or an EPI growth process (Par. 0059).
Regarding Claim 21, Miyazaki et al., as applied to claim 16, discloses the method, wherein the top surface of the island region is more proximal to the first surface of the semiconductor than the bottom surface of the island region (Fig. 1).
Regarding Claim 22, Miyazaki et al., as applied to claim 12, discloses the method, wherein the island region is doped by single peak doping or multi peak doping, and the shape of ion doping profile of the island region comprises at least one peak selected from the group consisting of: a triangle single peak, a quadrangle single peak, and irregular multi peaks (Fig. 1).
Regarding Claim 23, Miyazaki et al., as applied to claim 12, discloses the method wherein the position of the top surface of the island region is formed in a certain range, the position of the bottom surface of the island region is formed at WD, the method comprising: determining an implantation depth of the island region according to the width WD of the depletion region, and determining a proton implantation energy according to the corresponding relationship between the proton implantation energy and the implantation depth of the island region, so that the position of the top surface of the island region is formed in the certain range, and the position of the bottom surface of the island region is formed at WD (Par. 0059-0064, 0069-0078, 0095; Figs. 1-21 – implied).
Response to Arguments
Applicants’ arguments filed on 01/20/2026 have been fully considered but they are not found to be persuasive. More explanations are added to the rejection to clarify further Examiner’s position in response to the Applicant’s Arguments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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04/12/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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