Prosecution Insights
Last updated: April 19, 2026
Application No. 18/311,178

CALIBRATION OF QUANTUM PROCESSOR OPERATOR PARAMETERS

Non-Final OA §DP
Filed
May 02, 2023
Examiner
LANE, THOMAS BERNARD
Art Unit
2142
Tech Center
2100 — Computer Architecture & Software
Assignee
Google LLC
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
3y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
9 granted / 10 resolved
+35.0% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
18 currently pending
Career history
28
Total Applications
across all art units

Statute-Specific Performance

§101
33.9%
-6.1% vs TC avg
§103
38.3%
-1.7% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
16.1%
-23.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 10 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Application is a continuation of Patent No. US 9940212 B2, filed on 06/07/2019. Information Disclosure Statement The information disclosure statement (IDS) submitted on 07/17/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 2 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application A computer-implemented method for determining quantum processor operating parameters, the method comprising: A computer-implemented method comprising: represented by a graph comprising nodes and edges, wherein each node represents a respective qubit and is associated with a value representing an operating parameter of the respective qubit, and wherein each edge represents a respective interaction between two qubits and is associated with a value representing an operating parameter of the respective interaction;… for a quantum processor having a plurality of interacting qubits and represented by a graph comprising nodes and edges, wherein each node represents a respective qubit and is associated with a value representing an operating parameter of the respective qubit, and each edge represents a respective interaction between two qubits and is associated with a value representing an operating parameter of the respective interaction: …identifying, by a classical computing device, one or multiple disjoint subsets of nodes or one or multiple disjoint subsets of edges, wherein nodes in a subset of nodes are related via the traversal rule and edges in a subset of edges are related via the traversal rule; determining, by a classical computing device, calibrated values for nodes or edges in one or more disjoint subsets of nodes, wherein nodes in each disjoint subset of nodes are related via a node-traversal rule, determining, by a classical computing device, calibrated values for the nodes or edges in each subset, comprising, for each subset: selecting a seed node or a seed edge in the subset; stepwise, for the selected seed node or seed edge, and for each subsequent node or edge: performing a constrained optimization using i) an objective function for the node or edge, and ii) one or more constraints based on a calibrated operating parameter mapping comprising calibrated values of nodes or edges in the graph, to determine a calibrated value for the node or edge; the determining comprising, for each disjoint subset of nodes: selecting a seed node in the subset; stepwise, for the selected seed node, and for each subsequent node: performing a constrained optimization using i) an objective function for one or more nodes and one or more edges, and ii) one or more constraints based on calibrated values in the calibrated operating frequency mapping of calibrated nodes or edges within a local region of predetermined size around the node, to determine a calibrated value for the node and one or more edges that connect the node to an already calibrated node; determining whether each node or edge in the subset has been calibrated; determining whether each node or edge in the subset has been calibrated; in response to determining that each node or edge in the subset has not been calibrated, traversing the graph based on the traversal rule to select a subsequent node or edge for the step. and in response to determining that each node or edge in the subset has not been calibrated, traversing the graph based on a node-traversal rule to select a subsequent node for the step. Claim 3 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 1, further comprising storing the determined calibrated value in the calibrated operating parameter mapping. The method of claim 2, further comprising storing the determined calibrated value in the calibrated operating parameter mapping. Claim 4 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 1, wherein the traversal rule comprises an undirected traversal rule. The method of claim 2, wherein the node-traversal rule comprises an undirected node-traversal rule. Claim 5 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 1, further comprising, in response to determining that each node or edge in the subset has been calibrated: determining whether each node or edge in the graph has been calibrated; and in response to determining that each node or edge in the graph has been calibrated, setting the operating parameters of the quantum processor to the calibrated values included in the calibrated operating parameter mapping. The method of claim 2, further comprising, in response to determining that each node or edge in the subset has been calibrated, setting operating parameters of the quantum processor to the calibrated values included in the calibrated operating parameter mapping. Claim 6 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 1, further comprising: determining whether any calibrated values of nodes or edges have timed out; and in response to determining that a calibrated value of a node or edge has timed out: updating the calibrated frequency mapping; The method of claim 2, further comprising: determining whether any calibrated values of nodes or edges have timed out; and in response to determining that a calibrated value of a node or edge has timed out: updating the calibrated frequency mapping; discarding calibration values in a local region of predetermined size around the timed out calibrated value; maintaining calibrated values outside of the local region; and recalibrating the graph discarding calibration values in a local region of predetermined size around the timed out calibrated value; maintaining calibrated values outside of the local region; and recalibrating the graph. Claim 9 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 - 10 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 9, further comprising: selecting a graph traversal algorithm, wherein the graph traversal algorithm comprises an algorithm that traverses edges of the graph based on an edge traversal rule; The method of claim 2, further comprising: selecting a graph traversal algorithm, wherein the graph traversal algorithm comprises an algorithm that traverses edges of the graph based on an edge traversal rule; identifying one or more disjoint subsets of edges, wherein nodes and edges in each of the disjoint subsets are connected using the traversal rule; identifying one or more disjoint subsets of edges, wherein nodes and edges in each of the disjoint subsets are connected using the traversal rule; determining calibrated values of the edges in each subset, comprising, for each subset: selecting a seed edge in the subset; determining calibrated values of the edges in each subset, comprising, for each subset: selecting a seed edge in the subset; stepwise, for the selected seed edge, and for each subsequent edge: performing a constrained optimization using i) an objective function for the edge, and ii) one or more constraints based on a calibrated operating parameter mapping comprising calibrated values of edges in the graph, to determine a calibrated value for the edge; stepwise, for the selected seed edge, and for each subsequent edge: performing a constrained optimization using i) an objective function for the edge, and ii) one or more constraints based on a calibrated operating parameter mapping comprising calibrated values of edges in the graph, to determine a calibrated value for the edge; determining whether each edge in the subset has been calibrated; determining whether each edge in the subset has been calibrated; in response to determining that each edge in the subset has not been calibrated, traversing the graph based on the traversal rule to select a subsequent edge for the step. in response to determining that each edge in the subset has not been calibrated, traversing the graph based on the traversal rule to select a subsequent edge for the step. Claim 10 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 - 12 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 11, further comprising: selecting a graph traversal algorithm, wherein the graph traversal algorithm comprises an algorithm that traverses nodes of the graph based on an node traversal rule; determining a complete traversal set comprising one or more disjoint subsets of nodes, wherein nodes and edges in each of the disjoint subsets are connected using the traversal rule; The method of claim 2, further comprising: determining a complete traversal set comprising one or more disjoint subsets of nodes, wherein nodes and edges in each of the disjoint subsets are connected using the traversal rule; determining calibrated values of the nodes in each subset, comprising, for each subset: selecting a seed node in the subset; determining calibrated values of the nodes in each subset, comprising, for each subset: selecting a seed node in the subset; stepwise, for the selected seed node, and for each subsequent node: performing a constrained optimization using i) an objective function for the node, and ii) one or more constraints based on a calibrated operating parameter mapping comprising calibrated values of nodes in the graph, to determine a calibrated value for the node; stepwise, for the selected seed node, and for each subsequent node: performing a constrained optimization using i) an objective function for the node, and ii) one or more constraints based on a calibrated operating parameter mapping comprising calibrated values of nodes in the graph, to determine a calibrated value for the node; determining whether each node in the subset has been calibrated; in response to determining that each node in the subset has not been calibrated, traversing the graph based on the traversal rule to select a subsequent node for the step. Claim 11 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 1, wherein determining calibrated values of the nodes or edges in each subset is performed in parallel for each subset The method of claim 2, wherein determining calibrated values of the nodes or edges in each subset is performed in parallel for each subset. Claim 12 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 1, further comprising: separating the graph of nodes and edges into multiple subgraphs; The method of claim 2, further comprising: separating the graph into multiple subgraphs; determining calibrated values for nodes or edges in subsets of some or all of the multiple subgraphs in parallel; determining calibrated values for nodes or edges in subsets of some or all of the multiple subgraphs in parallel; recombining the subgraphs into the graph; determining whether the graph comprises one or more un-calibrated subgraphs; recombining the subgraphs into the graph; determining whether the graph comprises one or more un-calibrated subgraphs; and in response to determining that the graph comprises one or more un-calibrated subgraphs, calibrating the graph. and in response to determining that the graph comprises one or more un-calibrated subgraphs, calibrating the graph. Claim 13 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 1, wherein selecting the graph traversal algorithm comprises selecting the graph traversal algorithm based on the interactions between qubits in the quantum processor. The method of claim 2, further comprising selecting the node-traversal rule, comprising selecting the node-traversal rule based on the interactions between qubits in the quantum processor Claim 14 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application The method of claim 1, wherein the operating parameter of the respective qubit comprises an idling frequency, readout frequency, or interaction frequency of the respective qubit. The method of claim 2, wherein the operating parameter of the respective qubit comprises an idling frequency, readout frequency, or interaction frequency of the respective qubit. Claim 15 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of U.S. Patent No. US 9940212 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because Patent No. US 9940212 B2 Current Application An apparatus comprising one or more classical computers and one or more classical storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more classical computers to perform operations comprising: for a quantum processor having a plurality of interacting qubits, represented by a graph comprising nodes and edges, wherein each node represents a respective qubit and is associated with a value representing an operating parameter of the respective qubit, and wherein each edge represents a respective interaction between two qubits and is associated with a value representing an operating parameter of the respective interaction; selecting a graph traversal algorithm that traverses the graph based on a traversal rule; identifying one or multiple disjoint subsets of nodes or one or multiple disjoint subsets of edges, wherein nodes in a subset of nodes are related via the traversal rule and edges in a subset of edges are related via the traversal rule; determining calibrated values for the nodes or edges in each subset, comprising, for each subset: selecting a seed node or a seed edge in the subset; An apparatus comprising one or more classical computers and one or more classical storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more classical computers to perform operations comprising: for a quantum processor having a plurality of interacting qubits and represented by a graph comprising nodes and edges, wherein each node represents a respective qubit and is associated with a value representing an operating parameter of the respective qubit, and each edge represents a respective interaction between two qubits and is associated with a value representing an operating parameter of the respective interaction: determining, by a classical computing device, calibrated values for nodes or edges in one or more disjoint subsets of nodes, wherein nodes in each disjoint subset of nodes are related via a node-traversal rule, the determining comprising, for each disjoint subset of nodes: selecting a seed node in the subset; stepwise, for the selected seed node or seed edge, and for each subsequent node or edge: performing a constrained optimization using i) an objective function for the node or edge, and ii) one or more constraints based on a calibrated operating parameter mapping comprising calibrated values of nodes or edges in the graph, to determine a calibrated value for the node or edge; stepwise, for the selected seed node, and for each subsequent node: performing a constrained optimization using i) an objective function for one or more nodes and one or more edges, and ii) one or more constraints based on calibrated values in the calibrated operating frequency mapping of calibrated nodes or edges within a local region of predetermined size around the node, to determine a calibrated value for the node and one or more edges that connect the node to an already calibrated node; determining whether each node or edge in the subset has been calibrated; determining whether each node or edge in the subset has been calibrated; in response to determining that each node or edge in the subset has not been calibrated, traversing the graph based on the traversal rule to select a subsequent node or edge for the step. and in response to determining that each node or edge in the subset has not been calibrated, traversing the graph based on a node-traversal rule to select a subsequent node for the step. Allowable Subject Matter Claims 5, 7-8, and 16-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS B LANE whose telephone number is (571)272-1872. The examiner can normally be reached M-Th: 7am-5pm; F: Out of Office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARIELA REYES can be reached at (571) 270-1006. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS BERNARD LANE/Examiner, Art Unit 2142 /HAIMEI JIANG/Primary Examiner, Art Unit 2142
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Prosecution Timeline

May 02, 2023
Application Filed
Feb 18, 2026
Non-Final Rejection — §DP (current)

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Study what changed to get past this examiner. Based on 3 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+16.7%)
3y 11m
Median Time to Grant
Low
PTA Risk
Based on 10 resolved cases by this examiner. Grant probability derived from career allow rate.

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