DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election without traverse of Group I, Species II, claim 7, in the reply filed on 12/8/2025 is acknowledged.
Claims 7-11 are being examined in this Office Action.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 7-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, claim 7, line 11 cites “depositing gate dielectric layers between the semiconductor layers” is not clear because of “the semiconductors layers”. There is insufficient antecedent basis for this limitation in the claim. The claim does not clearly define when and where the semiconductor layers are formed during the process. As disclosed in the specification, claimed “multiple conductor layers” are made of semiconductor material & “a semiconductor” that is filled bit line holes. For examination purpose, either of one or both will be considered in as the semiconductor layers.
In claim 10, line 2 cites “an operation of depositing a semiconductor layer in the bit line holes before depositing the conductors to fill the bit line holes” is not clear because of “a semiconductor layer”. Claim 7 requires “deposing a semiconductor to fill the bit line holes”, it is not clear whether “a semiconductor layer” is same or different from “a semiconductor” in claim 1. For examination purpose, they are considered as a same material.
Claims 8, 9 & 11 are rejected as being dependent on claim 1.
Applicant is suggested to revise and clarify the claim(s) to avoid any further confusions.
For best understanding and examination purpose, the claims will be best considered based on drawings, disclosure, and/or any applicable prior arts.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Moriyama et al. (US 2020/0286815) in view of Endoh et al. (US 2013/0119452).
Re claim 1, Moriyama teaches, under BRI, Figs. 2, 12, 15-17 & 23 [0056-0057, 0107, 0108, 0117, 0118, 0130-0132, 0136], a memory cell structure, formed by a process of:
-alternately depositing multiple conductor layers (132 including first/second materials) and sacrificial layers (142) to form a stack (Fig. 2, [0056, 0057];
-forming vertical bit line holes (trenches 79, via cavity 379) through the stack using a deep trench process (e.g., anisotropic etch process) (Fig. 11A, [0107, 0108]);
-forming recesses (143, 243) in the conductor layers (132 including first/second materials) using an isotropic etching process through the bit line holes (79, 379) (Fig. 12, [0117-0118]);
-depositing a semiconductor (764L) to fill the bit line holes (79, 379) to form floating bodies (Fig. 15, [0130, 0131]);
-removing the semiconductor (764L) inside the bit line holes (79, 379) to reform the bit line holes (Fig. 16, [0135, 0136]);
-depositing conductors (766L, 768L) to fill the bit line holes (Fig. 17, [0130, 0136]);
-removing the sacrificial layers (142) (Figs. 11A-12, [0116]);
-depositing gate dielectric layers (752) between (in y-axis) the semiconductor layers (between semiconductor material 364 & 764) (Fig. 23, [0154]); and
-depositing gate material (754) onto the gate dielectric layers (752) (Fig. 23, [0154]).
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Moriyama further teaches a doped semiconductor material may be deposited in cavities (Fig. 9C, [0100]), but does not explicitly teach depositing the semiconductor to fill the recesses.
Endoh teaches, Figs. 3B-3C, [0189], depositing the semiconductor (16) to fill the recesses (between 14A & 14B).
As taught by Endoh, one of ordinary skill in the art would utilize & modify the above teaching into Moriyama to deposit the semiconductor to fill the recesses as claimed, because semiconductor material is known and wildly used in memory structures; and further it aids in reducing number of machining steps and reducing the cost per bit.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Endoh in combination with Moriyama due to above reason.
Re claim 8, Moriyama teaches wherein the isotropic etching process comprises a wet etching process [0117].
Re claim 9, Moriyama teaches wherein each of the conductors (766L, 768L) is one of metal (e.g., tungsten, [0130, 0136]) or polysilicon.
Re claim 10, Moriyama teaches, under BRI, Figs. 15-17, an operation of depositing a semiconductor layer (consider 764L) in the bit line holes (79, 379) before depositing the conductors (766L, 768L) to fill the bit line holes (79, 379).
5. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Moriyama as modified by Endoh as applied to claim 7 above, and further in view of Jeong et al. (US 2014/0120685).
The teachings of Moriyama/Endoh have been discussed above.
Re claim 11, Moriyama teaches an operation of forming drain regions (63) (Fig. 9D, [0101]) before depositing the conductors (766L, 768L) to fill the bit line holes.
Moriyama/Endoh does not teach using an isotropic doping process through the bit line holes.
Jeong teaches “the first ion-implanting process may include an ion-implantation method or a PLAD (Plasma Doping) method” [0028].
As taught by Jeong, one of ordinary skill in the art would utilize & modify the above teaching to obtain an operating of using isotropic doping process to form drain regions as claimed, because it aids in precisely & uniformly doping a material at a reduced time.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Jeong in combination with Moriyama/Endoh due to above reason.
Double Patenting
6. A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 7-11 are provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 7-11 of copending Application No. 18/544,393 (reference application). This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented.
Current application 18/311,212
7. A memory cell structure, formed by a process of:
alternately depositing multiple conductor layers and sacrificial layers to form a stack;
forming vertical bit line holes through the stack using a deep trench process;
forming recesses in the conductor layers using an isotropic etching process through the bit line holes;
depositing a semiconductor to fill the bit line holes and recesses to form floating bodies;
removing the semiconductor inside the bit line holes to reform the bit line holes;
depositing conductors to fill the bit line holes;
removing the sacrificial layers;
depositing gate dielectric layers between the semiconductor layers; and
depositing gate material onto the gate dielectric layers.
18/544,393
7. A memory cell structure, formed by a process of:
alternately depositing multiple conductor layers and sacrificial layers to form a stack;
forming vertical bit line holes through the stack using a deep trench process;
forming recesses in the conductor layers using an isotropic etching process through the bit line holes;
depositing a semiconductor to fill the bit line holes and recesses to form floating bodies;
removing the semiconductor inside the bit line holes to reform the bit line holes; depositing conductors to fill the bit line holes;
removing the sacrificial layers; depositing gate dielectric layers between the semiconductor layers; and
depositing gate material onto the gate dielectric layers.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/10/26