DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 5 in the reply filed on 10/7/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11-14 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Park et al (US 2020/0098719).
1. A semiconductor package comprising:
a first semiconductor chip (Fig.1 (100A) and [0021]/Fig.5 (300) and [0068-0069/0061]) comprising through silicon vias (TSVs) (Fig.1 (130) and [0029]/Fig.5 (not shown but described [0069]), wherein respective upper conductive pads (Fig.1 (144) and [0029]/Fig.5 (330) and [0069]) are electrically connected to the TSVs (Fig.1 (130) and [0029]/Fig.5 (not shown but described [0069]) and are on an upper surface of the first semiconductor chip (Fig.1 (100A) and[ 0021]/Fig.5 (300) and [0068-0069/0061]);
a second semiconductor chip (Fig.1(100B) and [0021]/Fig.5 (100A) and [0071]) on the first semiconductor chip (Fig.1 (100A) and [0021]/Fig.5 (300) and [0068-0069/0061]), wherein lower conductive pads (Fig.1/5 (142) and [0029]) are on a lower surface of the second semiconductor chip (Fig.1(100B) and [0021]/Fig.5 (100A) and [0071]);
conductive bumps (Fig.1/5 (170A/B) and [0029]) between the upper conductive pads (Fig.1 (144) and [0029]/Fig.5 (330) and [0069]) and the lower conductive pads (Fig.1/5 (142) and [0029]);
an interlayer adhesive layer (Fig.1 (150) and [0040/0047])/Fig.5(160) and [0075- teaching that 160 and 150 may be the same material]) between the first semiconductor chip (Fig.1 (100A) and [0021]/Fig.5 (300) and [0068-0069/0061]) and the second semiconductor chip (Fig.1(100B) and [0021]/Fig.5 (100A) and [0071]); and
an encapsulant (Fig.1/5 (180) and [0041]) on a side surface of the second semiconductor chip (Fig.1(100B) and [0021]/Fig.5 (100A) and [0071], wherein, an interlayer space (Fig.1/5 (CS/CS1) and [0051]) is between the first semiconductor chip (Fig.1 (100A) and [0021]/Fig.5 (300) and [0068-0069/0061]) and the second semiconductor chip (Fig.1(100B) and [0021]/Fig.5 (100A) and [0071]) and overlaps the first semiconductor chip (Fig.1 (100A) and [0021]/Fig.5 (300) and [0068-0069/0061]) and the second semiconductor chip (Fig.1(100B) and [0021]/Fig.5 (100A) and [0071]) in a vertical direction that is perpendicular to the upper and lower surfaces of both the first semiconductor chip (Fig.1 (100A) and [0021]/Fig.5 (300) and [0068-0069/0061]) and the second semiconductor chip (Fig.1(100B) and [0021]/Fig.5 (100A) and [0071]), and wherein the encapsulant (Fig.1/5 (180) and [0041]) extends into the interlayer space (Fig.1/5 (CS/CS1) and [0051]).
11. The semiconductor package of claim 1, wherein the encapsulant (Fig.1/5 (180) and [0041]) extends into the interlayer space (Fig.1/5 (CS/CS1) and [0051]) and is in contact with a portion of the upper surface of the first semiconductor chip (Fig.1 (100A) and [0021]/Fig.5 (300) and [0068-0069/0061]) and in contact with a portion of the lower surface of the second semiconductor chip (Fig.1(100B) and [0021]/Fig.5 (100A) and [0071]).
12. The semiconductor package of claim 1, wherein the interlayer adhesive layer comprises a non-conductive film (Fig.1 (150) and [0040/0047])/Fig.5(160) and [0075- teaching that 160 and 150 may be the same material]).
13. The semiconductor package of claim 1, wherein the encapsulant comprises epoxy molding compound (EMC) (Fig.1/5 (180) and [0041]).
14. The semiconductor package of claim 1, further comprising: an upper semiconductor chip (Fig.5 (100B) and [0072]) on the second semiconductor chip (Fig.5 (100A) and [0071]) and having a thickness greater than a thickness of the first semiconductor chip Fig.5 (300) and [0068-0069/0061]) or a thickness of the second semiconductor chip (See Fig.5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al (US 10930613); Kim et al (US 11164805); Lu et al (US 9184153) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
1/4/26
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