DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Drawings
The drawings filed on 05/03/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 05/03/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Aleksov (US 2022/0189861).
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Regarding claim 1, Aleksov (US 2022/0189861) discloses:
A semiconductor package, comprising:
an interposer including a first redistribution layer (114, ¶0030) and a second redistribution layer (112, ¶030) that is on the first redistribution layer (114) and is electrically coupled to the first redistribution layer (114, ¶0030); and
a semiconductor chip (102-1, ¶0022) on the interposer, wherein the first redistribution layer (114) includes a first organic insulating layer (106 corresponding to 114, ¶0030, lines 32-34) and a plurality of first conductors (114) in the first organic insulating layer (106), wherein the second redistribution layer (112) includes a second organic insulating layer (106 corresponding to 112), a first silicon insulating layer (108, ¶0025) on the second organic insulating layer (106), and a plurality of second conductors (portions of 110 in layers 108, 107-2 and 106 of interposer 150) penetrating through both of the second organic insulating layer (106) and the first silicon insulating layer (108), wherein the semiconductor chip (102-1) includes a second silicon insulating layer (108, ¶0025) and a plurality of third conductors (110) in the second silicon insulating layer (108), and wherein each second conductor (110) of the plurality of second conductors is directly bonded to a separate, respective third conductor (110) of the plurality of third conductors, and wherein the first silicon insulating (108) layer is directly bonded to the second silicon insulating layer (108, ¶0024, ¶0025, ¶0053).
Regarding claim 2, Aleksov further discloses:
wherein a level of an uppermost surface of the plurality of second conductors (110) and a level of an uppermost surface of the first silicon insulating layer (108) are substantially a same level (figure 2).
Regarding claim 3, Aleksov further discloses:
wherein both of the first silicon insulating layer (108) and the second silicon insulating layer (108) include a silicon oxide (¶0025).
Regarding claim 4, Aleksov further discloses:
wherein both of the plurality of second conductors and the plurality of third conductors include copper (Cu) (¶0024) .
Regarding claim 5, Aleksov further discloses:
wherein the interposer (150, 106) comprises an organic interposer (¶0030).
Regarding claim 6, Aleksov further discloses:
wherein each of the first organic insulating layer and the second organic insulating layer (108) includes a photo imageable dielectric (PID) (¶0052).
Allowable Subject Matter
Claims 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art does not disclose “wherein the second redistribution layer further includes barrier metal layers, and the barrier metal layers are interposed between the plurality of second conductors and a stack that includes both of the second organic insulating layer and the first silicon insulating layer” in combination with the remaining claimed features..
Claims 9-20 are allowed.
Regarding claim 9, the prior art does not disclose “ barrier metal layers that are interposed at interfaces between the plurality of second conductors and a stack that includes both of the second organic insulating layer and the first silicon insulating layer” in combination with the remaining claimed features.
Regarding claim 13, the prior art does not disclose “forming a barrier metal layer on an upper surface and sidewalls of the organic insulating layer; forming a second seed metal layer on both of the first seed metal layer and the barrier metal layer; forming a plurality of first conductors on the second seed metal layer in the plurality of openings of the organic insulating layer; removing both of the barrier metal layer and the second seed metal layer above the upper surface of the organic insulating layer; forming a redistribution layer on both of the upper surface of the organic insulating layer and an upper surface of the first conductors” in combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899
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