DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-18 and 26-27 in the reply filed on 12/19/2025 is acknowledged. Claims 19-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and Species, here being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/19/2025.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202210560680.7, filed on 05/19/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/27/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the "portions where the first active layer is adjacent to the second active layer are substantially aligned in the vertical direction," "portions where an outer sidewall of the first active layer is adjacent to an outer sidewall of the second active layer are substantially coplanar in the vertical direction," "the vertically extending portion of the first active layer is substantially aligned with the vertical extending portion of the second active layer in the vertical direction," and "the vertical extending portion of the first active layer, the vertical extending portion of the second active layer, and an outer sidewall of the isolation portion are substantially coplanar in the vertical direction." must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The term “substantially aligned” in claim 1 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In claim 1, wherein portions where the first active layer is adjacent to the second active layer are substantially aligned in the vertical direction is not definite since substantially aligned is not clearly defined.
The term “substantially ” in claim 2 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In claim 2, wherein portions where an outer sidewall of the first active layer is adjacent to an outer sidewall of the second active layer are substantially coplanar in the vertical direction is not definite since substantially coplanar is not clearly defined.
The term “substantially aligned” in claim 9 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In claim 9, .
The term “substantially ” in claim 13 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In claim 13, the vertical extending portion of the second active layer, and an outer sidewall of the isolation portion are substantially coplanar in the vertical direction is not definite since substantially coplanar is not clearly defined.
The term “relatively high mobility, relatively low leakage, and relatively large bandgap width” in claim 15 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In claim 15, the first active layer comprises a semiconductor material with a relatively high mobility, and the second active layer comprises a semiconductor material with a relatively low leakage or a relatively large bandgap width is not definite since relatively high mobility, relatively low leakage, and relatively large bandgap width are not clearly defined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-6, 8-11, 16, 18, and 26 are rejected under 35 U.S.C. 102 as being anticipated by Sano et al. ( US 9,673,304 B1; hereinafter Sano )
Regarding claim 1, Sano teaches a memory device ( Figs. 3A-3E: monolithic three-dimensional memory array #300 ), comprising: a first connection line layer ( Fig. 3A: GBL ) , a second connection line layer ( Fig. 3A: LBL ), and a third connection line layer ( Fig. 3A: WL) that are sequentially disposed in a vertical direction ( as shown in Fig. 3A ) with respect to a substrate ( Fig. 3A #302 ), wherein the first connection line layer ( Fig. 3A: GBL ) comprises a plurality of first conductive lines extending parallel to each other in a first direction ( Col. 6 lines 56-58 The global bit lines GBL.sub.1-GBL.sub.3 are arranged in a third direction (e.g., a y-direction) that is perpendicular to both the first direction and the second direction ), the second connection line layer ( Fig. 3A: LBL.sub.11 ) comprises a plurality of second conductive lines extending parallel to each other in a second direction intersecting the first direction ( as shown in Fig. 3A ), and the third connection line layer ( Fig. 3A: WL ) comprises a plurality of third conductive lines extending parallel to each other in the first direction ( as described above ); a plurality of memory cells ( Fig. 3A: M.sub.111 – M.sub.536 ), wherein each memory cell extends vertically from a corresponding first conductive line in the first connection line layer ( as shown in Fig. 2A: GBL.sub.1 ) and passes through a corresponding second conductive line in the second connection line layer ( Fig. 2A: :LBL.sub.11 ) and a corresponding third conductive line in the third connection line layer ( Fig. 3A WL ), and each memory cell comprises a first transistor and a second transistor that are stacked on each other in the vertical direction ( Col. 11 lines 34-36 Vertically-oriented bit line select transistors Q.sub.11 – Q.sub.33 may be used to select a corresponding one of vertical bit lines LBL.sub.11 – LBL.sub.33 ), wherein the first transistor ( Q.sub.11 as discussed above ) comprises: a first active layer ( Fig. 4A1: #402 ), comprising a first source/drain region electrically connected ( Col. 10 lines 7 – 14 Each of vertically-oriented bit line select transistors Q.sub.11-Q.sub.33 has a first terminal 312a (e.g., a drain/source terminal), a second terminal 312b (e.g., a source/drain terminal), a first control terminal 312c1 (e.g., a first gate terminal) and a second control terminal 312c2 (e.g., a second gate terminal) ) with the corresponding first conductive line in the first connection line layer ( Fig. 3A: GBL.sub.1 ), a second source/drain region electrically connected ( Col. 7 line 64 – Col. 8 line 2 The local bit line (e.g., LBL.sub.11) coupled to the selected memory cell (M.sub.111) is biased to a selected bit line voltage in read mode (e.g., 1 V) via the associated bit line select transistor (e.g., Q.sub.11) coupled to the selected local bit line (LBL.sub.11), and the global bit line (e.g., GBL.sub.1) coupled to the bit line select transistor (Q.sub.11) ) with the corresponding second conductive line in the second connection line layer ( Fig. 3A: LBL.sub.11 ), and a channel region transistor ( Col. 10 lines 19-24 First gate terminal 312c1 may be used to selectively induce a first conductive channel between first terminal 312a and second terminal 312b of the transistor ) between the first source/drain region ( as discussed above) of the first and the second source/drain region of the first transistor ( as discussed above ); a first gate dielectric layer ( Col. 10 lines 14-18 A gate dielectric material #314 is disposed between first gate terminal 312c1 and first terminal 312a and second terminal 312b and also is disposed between second gate terminal 312c2 and first terminal 312a and second terminal 312b ) on the first active layer ( Fig. 4A1 #402 ); and a first gate conductor layer on the first gate dielectric layer ( Col. 10 lines 14 – 18 A gate dielectric material #314 is disposed between first gate terminal #312c1 and first terminal #312a ), and wherein the second transistor comprises ( Fig. 2A Q.sub.21 ) : a second active layer ( Fig. 4A1 #406 ), comprising a first source/drain region electrically connected with the first gate conductor layer ( as discussed above ), a second source/drain region electrically connected with the corresponding third conductive line in the third connection line layer ( Fig. 3A: WL connections ), and a channel region between the first source/drain region of the second transistor and the second source/drain region of the second transistor ( as discussed above) , wherein portions where the first active layer is adjacent to the second active layer are substantially aligned in the vertical direction; a second gate dielectric layer on the second active layer ( as discussed above) ; and a second gate conductor layer on the second gate dielectric layer ( Col. 10 lines 14-18 second terminal #312b, and also is disposed between second gate terminal #312c2 and first terminal #312a and second terminal #312b); and a fourth connection line layer ( Fig. 2A SG.sub.N )above the memory cell, comprising a plurality of fourth conductive lines extending in the second direction ( as shown in Fig. 2A ), wherein the second gate conductor layer of each memory cell is electrically connected to a corresponding fourth conductive line in the fourth connection line layer ( as shown in Fig. 2A ).
Regarding claim 2, Sano teaches the memory device according to claim 1 ( as discussed above) , wherein portions where an outer sidewall of the first active layer ( Fig. 4A1 #402 ) is adjacent to an outer sidewall of the second active layer ( Fig. 4A1 #406 ) are substantially coplanar in the vertical direction ( as shown in Fig. 4A1 ).
Regarding claim 3, Sano teaches the memory device according to claim 1 ( as discussed above), wherein the first active layer ( Fig. 4A1 #402 ) has a bottom portion ( as shown in Fig. 4A1 ) and a vertical extending portion extending vertically upward from the bottom portion ( as show in Fig. 4A1 ), wherein the bottom portion ( Fig. 4A1 #402 ) is in physical contact with the corresponding first conductive line in the first connection line layer ( Fig. GBL.sub.1 ), and the vertical extending portion ( Fig. 4A1 #314 ) is in physical contact with the corresponding second conductive line in the second connection line layer ( Col. 7 line 64 – Col. 8 line 2 The local bit line (e.g., LBL.sub.11) coupled to the selected memory cell (M.sub.111) is biased to a selected bit line voltage in read mode (e.g., 1 V) via the associated bit line select transistor (e.g., Q.sub.11) coupled to the selected local bit line (LBL.sub.11), and the global bit line (e.g., GBL.sub.1) coupled to the bit line select transistor (Q.sub.11) ).
Regarding claim 4, Sano teaches the memory device according to claim 3 (as discussed above ), wherein the first gate dielectric layer ( Fig. 4A1 #314 ) extends along an inner wall of the first active layer ( Fig. 4A1 #402 ), and an inner space of the first gate dielectric layer ( Fig. 4A1 #314 ) is filled with the first gate conductor layer ( Fig. 4A1 #404 ).
Regarding claim 5, Sano teaches the memory device according to claim 3 (as discussed above ), wherein the second active layer has a bottom portion ( Fig. 4A1 #406 ) and a vertical extending portion extending vertically upward ( Fig. 4A1 #314 ) from the bottom portion of the second active layer ( Fig. 4A1 #406 ), wherein the bottom portion of the second active layer ( Fig. 4A1 #406 ) is electrically connected with the first gate conductor layer ( Fig. 4A1 #404 ), and the vertical extending portion of the second active layer ( Fig. 4A1 #314 ) is in physical contact with the corresponding third conductive line in the third connection line layer ( Fig. 3A WL connections ).
Regarding claim 6, Sano teaches the memory device according to claim 5 ( as discussed above), wherein the bottom portion of the second active layer ( Fig. 4A1 #406 ) is in physical contact with the first gate conductor layer ( Fig. 4A1 #404 ).
Regarding claim 8, Sano teaches the memory device according to claim 5 ( as discussed above), wherein the second gate dielectric layer (Col. 10 lines 14-18 second terminal #312b, and also is disposed between second gate terminal #312c2 and first terminal #312a and second terminal #312b ) extends along an inner wall of the second active layer ( Fig. 4A1 #406 ), and an inner space of the second gate dielectric layer is filled with the second gate conductor layer ( Fig. 4A1 #404 ).
Regarding claim 9, Sano teaches the memory device according to claim 5 ( as discussed above), wherein the vertical extending portion of the first active layer ( Fig. 4A1 #402 ) is substantially aligned with the vertical extending portion of the second active layer ( Fig. 4A1 #406 ) in the vertical direction ( as shown in Fig. 4A1 these layers are vertically aligned ).
Regarding claim 10, Sano teaches the memory device according to claim 5 ( as discussed above), further comprising: a gate length control layer ( Fig. 2A: SG.sub.1 ) between the second connection line layer ( Fig. 3A: LBL.sub.11 ) and the third connection line layer ( Fig. 3A: GBL.sub.2 ), wherein the gate length control layer comprises a gate length control pad ( Fig. 3A: SG.sub.1 ) disposed around the memory cell ( Fig. 1F ), and a lowest part of a bottom surface of the second gate conductor layer ( Fig. 4A1 #404 ) is lower than a top surface of the gate length control pad ( as shown in Fig. 4A1 ).
Regarding claim 11, Sano teaches the memory device according to claim 7 ( as discussed above), further comprising: a gate length control layer ( Fig. 2A: SG.sub.1 ) between the second connection line layer ( Fig. 3A: LBL.sub.11 ) and the third connection line layer ( Fig. 3A: GBL.sub.2 ), wherein the gate length control layer comprises a gate length control pad ( Fig. 3A: SG.sub.1 ) disposed around the memory cell ( Fig. 1F ), a bottom surface of the second gate conductor layer ( Fig. 4A1 #404 ) is at a vertical height between a top surface of the gate length control pad ( Fig. 3A SG.sub.1 ) and a bottom surface of the gate length control pad ( as shown in Fig. 4A1 ), and a top surface of the connection portion is not lower than the bottom surface of the gate length control pad ( as shown in Fig. 4A1 ).
Regarding claim 16, Sano teaches the memory device according to claim 1 ( as discussed above), wherein the first active layer ( Fig. 4A1 #402 )and the second active layer ( Fig. 4A1 #406 ) are self-aligned in the vertical direction ( as shown in Fig. 4A1 ).
Regarding claim 18, Sano teaches the memory device according to claim 1 ( as discussed above), wherein the memory device is a dynamic random access memory, the first conductive line ( Fig. 4A1: GBL.sub.1 ) corresponds to one of a read word line and a read bit line ( Col. 7 line 60 – Col. 8 line 8 In an embodiment of a read operation, the data stored in a selected memory cell (e.g., memory cell M.sub.111) may be read by biasing the word line connected to the selected memory cell (e.g., selected word line WL.sub.10) to a selected word line voltage in read mode (e.g., 0V). The local bit line (e.g., LBL.sub.11) coupled to the selected memory cell (M.sub.111) is biased to a selected bit line voltage in read mode (e.g., 1 V) via the associated bit line select transistor (e.g., Q.sub.11) coupled to the selected local bit line (LBL.sub.11), and the global bit line (e.g., GBL.sub.1) coupled to the bit line select transistor (Q.sub.11). A sense amplifier may then be coupled to the selected local bit line (LBL.sub.11) to determine a read current I.sub.READ of the selected memory cell (M.sub.111). The read current I.sub.READ is conducted by the bit line select transistor Q.sub.11, and may be between about 100 nA and about 500 nA, although other read currents may be used), the second conductive line corresponds to the other of the read word line and the read bit line, the third conductive line corresponds to a write bit line, and the fourth conductive line corresponds to a write word line ( Col. 8 lines 23-35 During the write operation described above, the word line (e.g., WL.sub.20) connected to the selected memory cell (M.sub.221) may be referred to as a “selected word line,” and the local bit line (e.g., LBL.sub.21) coupled to the selected memory cell (M.sub.221) may be referred to as the “selected local bit line.” All other word lines coupled to unselected memory cells may be referred to as “unselected word lines,” and all other local bit lines coupled to unselected memory cells may be referred to as “unselected local bit lines.” For example, if memory cell M.sub.221 is the only selected memory cell in memory array 200, word lines WL.sub.10-WL.sub.13 and WL.sub.21-WL.sub.23 are unselected word lines, and local bit lines LBL.sub.11, LBL.sub.31, LBL.sub.12-LBL.sub.32, and LBL.sub.13-LBL.sub.33 are unselected local bit lines ) .
Regarding claim 26, Sano teach an electronic apparatus ( Col. 17 line 58 – Col. 18 line 7 One embodiment of the disclosed technology includes an apparatus including forming a stack of sacrificial material layers above a substrate, etching the stack of sacrificial material layers to form rows of sacrificial material layers, forming a dielectric material between the rows of sacrificial material layers, forming a plurality of holes in the dielectric material, the holes disposed between the rows of sacrificial material layers, removing the rows of sacrificial material layers via the plurality of holes to form a plurality of cavities, forming a conductive material in each of the cavities to form a plurality of word line layers, forming a nonvolatile memory material on a sidewall of each of the plurality of holes, forming a plurality of local bit lines in the plurality of holes, and forming an array of memory cells, each memory cell comprising the nonvolatile memory material at an intersection of one of the plurality of local bit lines and one of the plurality of word line layers ), comprising the memory device according to claim 1 (as discussed above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Sano et al.; US 9,673,304 B1; 07/2016 in view of Lee et al.; US 2023/0020789 A1; ( CON of application filed 12/2020 )
Claim 7: Sano discloses the memory device according to claim 5 ( as discussed above).
Sano does not appear to disclose the memory cell further comprises: a connection portion between the first transistor and the second transistor, wherein the bottom portion of the second active layer is electrically connected with the first gate conductor layer through the connection portion.
However, Lee teaches the memory cell further comprises: a connection portion between the first transistor ( Fig. 2: word line layer #12p TSG layer ) and the second transistor ( Fig. 2: word line layer #12a BSG layer ), wherein the bottom portion of the second active layer is electrically connected with the first gate conductor layer through the connection portion ( [0050] Thus gate voltages can be applied on gates of the memory cells through the word line contacts #22 that are coupled to the word line layers #12a-#12p ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Sano to implement the memory cell further comprises: a connection portion between the first transistor and the second transistor, wherein the bottom portion of the second active layer is electrically connected with the first gate conductor layer through the connection portion because this controls current flow that may allow faster reads/writes.
Claims 12 and 13 are rejected under U.S.C. 103 as being unpatentable over Sano et al.; US 9,673,304 B1; 07/2016 in view of Su et al.; US 2022/0359026 A1; ( CON filed on 04/2020 )
Claim 12: Sano discloses the memory device according to claim 5 ( as discussed above ).
Sano does not appear to disclose the memory cell further comprises: an isolation portion in a form of spacer between the first active layer and the second active layer
However, Su teaches the memory cell further comprises: an isolation portion in a form of spacer between the first active layer and the second active layer ( [0021] In some embodiments, sidewall spacers are formed on sidewalls of the gate structures ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Su with Sano to implement the memory cell further comprises: an isolation portion in a form of spacer between the first active layer and the second active layer because this prevents electrical shorts, reduces interference, and improves device endurance.
Claim 13: Sano and Su disclose the memory device according to claim 12 ( as discussed above).
Sano does not appear to disclose the vertical extending portion of the first active layer, the vertical extending portion of the second active layer, and an outer sidewall of the isolation portion are substantially coplanar in the vertical direction.
However, Su teaches the vertical extending portion of the first active layer, the vertical extending portion of the second active layer, and an outer sidewall of the isolation portion are substantially coplanar in the vertical direction ( as shown in Fig. 1 the sidewalls are formed on the vertical gate structures #108, #110, #112, etc. )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Su with Sano to implement the vertical extending portion of the first active layer, the vertical extending portion of the second active layer, and an outer sidewall of the isolation portion are substantially coplanar in the vertical direction because this facilitates self-aligned fabrication and ensures uniform electrical performance.
Claims 14, 15, and 27 are rejected under U.S.C. 103 as being unpatentable over Sano et al.; US 9,673,304 B1; 07/2016 in view of Karda et al.; US 11,950,426 B2; ( DIV filed 10/2021)
Claim 14: Sano discloses the memory device according to claim 1 ( as discussed above).
Sano does not appear to disclose at least one of the first active layer and the second active layer comprises indium gallium zinc oxide.
However, Karda teaches at least one of the first active layer and the second active layer comprises indium gallium zinc oxide ( Col. 15 lines 21- 60 Material #520 can form a source, a drain, and a channel region. As an example, material 520 can include at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO.sub.x), indium gallium zinc oxide (IGZO))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Karda with Sano to implement at least one of the first active layer and the second active layer comprises indium gallium zinc oxide because this material has excellent semiconducting properties.
Claim 15: Sano discloses the memory device according to claim 1 ( as discussed above).
Sano does not appear to disclose the first active layer comprises a semiconductor material with a relatively high mobility, and the second active layer comprises a semiconductor material with a relatively low leakage or a relatively large bandgap width.
However, Karda teaches the first active layer comprises a semiconductor material with a relatively high mobility ( Col. 15 lines 21- 60 Material #520 can form a source, a drain, and a channel region. As an example, material #520 can include at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO); all of these materials have high electron mobility ), and the second active layer comprises a semiconductor material with a relatively low leakage or a relatively large bandgap width ( IGZO has low leakage, SnO2 and ZnO possess wide bandgaps and are included in the list of materials for material #520 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Karda with Sano to implement the first active layer comprises a semiconductor material with a relatively high mobility, and the second active layer comprises a semiconductor material with a relatively low leakage or a relatively large bandgap width because these material choices optimize device performance by pairing a fast channel with a robust, low-leakage barrier for efficient operation.
Claim 27: Sano discloses the electronic apparatus according to claim 26 ( as discussed above).
Sano does not appear to disclose the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.
However, Karda teaches the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply ( Col 31 lines 35-50 The memory devices (e.g., memory devices 100, 200, 800, 900, 2300, and 2800) described herein may be included in apparatuses (e.g., electronic circuitry) such as high-speed computers, communication and signal processing circuitry, single- or multi-processor modules, single or multiple embedded processors, multicore processors, message information switches, and application-specific modules including multilayer, multichip modules. Such apparatuses may further be included as subcomponents within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Karda with Sano to implement the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply because these devices commonly rely on memory devices to operate.
Claims 17 is rejected under U.S.C. 103 as being unpatentable over Sano et al.; US 9,673,304 B1; 07/2016 in view of Karda et al.; US 11,950,426 B2; ( DIV filed 10/2021) as it applies to claim 16, and further in view of Su et al.; US 2022/0359026 A1; ( CON filed on 04/2020 )
Claim 17: Sano and Karda disclose the memory device according to claim 16 ( as discussed above).
Neither Sano nor Karda appear to disclose the memory cell further comprises: an isolation portion in a form of spacer between the first active layer and the second active layer, wherein the first active layer, the second active layer, and the isolation portion are self-aligned in the vertical direction.
However, Su teaches the memory cell further comprises: an isolation portion in a form of spacer between the first active layer and the second active layer ( [0021] In some embodiments, sidewall spacers are formed on sidewalls of the gate structures ), wherein the first active layer, the second active layer, and the isolation portion are self-aligned in the vertical direction ( as shown in Fig. 1 the sidewalls are formed on the vertical gate structures #108, #110, #112, etc. )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Su with Sano and Karda to implement the memory cell further comprises: an isolation portion in a form of spacer between the first active layer and the second active layer, wherein the first active layer, the second active layer, and the isolation portion are self-aligned in the vertical direction because this improves cell density, enhances charge control and prevents cell-to-cell interference.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817