Attorney Docket Number: C5858-542
Filing Date: 5/04/2023
Claimed Priority Date: 05/31/2021 (CON of PCT/CN2021/097291)
Inventor: Zhai
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 5/04/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Claim Interpretation
Claim 12 contains a line reading “…the LED chip is disposed on a side face of the planarization layer away from the display backplane…”, which will be interpreted as “…the LED chip is disposed over a side face of the planarization layer away from the display backplane…”.
Claim Objection
Claim 12 is objected to because of the following informalities: Claim 12 recites the limitation “…a light-emitting diode (LED) chip…”, but this limitation was already introduced in the independent claim 12. For the purposes of examination, this limitation will be interpreted as “…the LED chip…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “…size…”. There is no antecedent basis for this claim.
Claim 5 also recites the limitation “…space…”. There is no antecedent basis for this claim.
Claim 5 also recites the limitation “…diameter…”. There is no antecedent basis for this claim.
The examiner believes that a typographical mistake was introduced and claim 5 was meant to depend from claim 4, which would resolve the 112b issues raised supra.
Accordingly, for the purpose of examination, claim 5 will be construed as reciting “The display backplane assembly of claim 4…”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (CN 112652697 A) in view of Gang (US 20210066368 A1).
Regarding claim 1, Zhang (see, e.g., fig. 1) shows most aspects of the instant invention, including a display backplane assembly comprising:
A display backplane (e.g., substrate 1), the display backplane having a first surface (e.g., upper surface of substrate 1), an electrode connecting pad (e.g., conductive metal layer 2) being disposed on the first surface (e.g., upper surface of substrate 1), and
A planarization layer (e.g., planarization layer 3) stacked on the first surface (e.g., upper surface of substrate 1), wherein the planarization layer (e.g., planarization layer 3) defines an accommodating hole (e.g., through hole 5) extending in a thickness direction (e.g., vertical direction) of the planarization layer (e.g., planarization layer 3), wherein the accommodating hole (e.g., through hole 5) corresponds to the electrode connecting pad (e.g., conductive metal layer 2), the accommodating hole (e.g., through hole 5) comprises a first hole (e.g., through hole 5), wherein the first hole (e.g., through hole 5) extends through the planarization layer (e.g., planarization layer 3) in the thickness direction (e.g., vertical direction) so that the electrode connecting pad (e.g., conductive metal layer 2) is at least partially exposed relative to the planarization layer (e.g., planarization layer 3), and a bonding material (e.g., bonding metal layer 6) is filled in the first hole (e.g., through hole 5) and in contact with the electrode connecting pad (e.g., conductive metal layer 2).
The bonding material (e.g., bonding metal layer 6) is used to electrically connect an electrode of a light-emitting diode (LED) chip (e.g., light-emitting diode 9) with the electrode connecting pad (e.g., conductive metal layer 2)
Zhang (see, e.g., fig. 1), however, fails to explicitly show numerous electrodes connecting pads and a plurality of the accommodating holes, while it also fails to show this plurality of accommodating holes comprises a second hole, wherein the second hole extends through at least a side face of the planarization layer away from the display backplane, and an adhesive is filled in the second hole, and the adhesive is used to adhere the LED chip to the planarization layer.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to duplicate the electrode connecting pads and accommodating holes of Zhang in order to the conductive connections necessary within the planarization layer, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Zhang (see, e.g., fig. 1), however, fails to show the plurality of accommodating holes comprises a second hole, wherein the second hole extends through at least a side face of the planarization layer away from the display backplane, and an adhesive is filled in the second hole, and the adhesive is used to adhere the LED chip to the planarization layer.
Gang (see, e.g., fig. 2) in a similar device to Zhang, teaches an adhesive material (e.g., adhesive layer 300), used to adhere a chip (e.g., semiconductor chip 100) to a planarization layer (e.g., flat glass pattern 600).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the adhesive material of Gang within at least some of the duplicated accommodating holes of Zhang, in order to adhere the LED chip to the other layers of the device as needed (see, e.g., paragraph 25 of Gang). Note that the LED chip lies on the planarization layer surface on the opposite side of the display backplane, and the duplicated accommodating holes (through hole 5 of Gang) extend through this side away from the display backplane.
Regarding claim 2, Zhang (see, e.g., fig. 1) shows wherein the electrode of the LED chip (e.g., light-emitting diode 9) is in non-fixed connection with the electrode connecting pad (e.g., conductive metal layer 2).
Regarding claim 3, Zhang in view of Gang teaches fails to teach wherein the first holes and second holes are alternately arranged at intervals in a direction perpendicular to the thickness direction of the planarization layer.
However, Gang (see, e.g., fig. 2) teaches the adhesive materials (e.g., adhesive layer 300) on opposite sides of the semiconductor chip (e.g., first semiconductor chip 100).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the separated horizontal adhesive configuration of Gang within the accommodating hole setup of Zhang, in order to provide adhesives across multiple of regions of the semiconductor chip (see, e.g., fig. 2 or paragraph 25 of Gang) alternating with the conductive bonding layers, as necessary.
Regarding claim 6, Zhang (see, e.g., fig. 1) shows a diameter (see, e.g., bottom diameter in annotated fig. 1 below) of the accommodating hole (e.g., through hole 5) at the one end close to the display backplane (e.g., substrate 1) is smaller than the diameter (see, e.g., top diameter in annotated fig. 1 below) of the accommodating hole (e.g., through hole 5) at the other end away from the display backplane (e.g., substrate 1).
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Annotated Fig. 1
Regarding claim 8, Zhang (see, e.g., fig. 1) shows the bonding material (e.g., bonding metal layer 6) exceeds the surface (e.g., note that bonding metal layer 6 extends through surface of planarization layer 3) of the planarization layer (e.g., planarization layer 3) away from the display backplane (e.g., substrate 1).
Regarding claim 10, Zhang (see, e.g., fig. 1) shows wherein the planarization layer (e.g., planarization layer 3) is made of at least one of polymethyl methacrylate, polystyrene, a polymer derivative with a phenolic group, an acrylic polymer, an imide-based polymer (see, e.g., paragraph text “Preferably, the planarization layer 3 is made of polyimide (PI)”), an arylether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, or a vinyl alcohol-based polymer.
Regarding claim 12, Zhang (see, e.g., fig. 1) shows most aspects of the instant invention, including a light-emitting diode (LED) display module, comprising:
an LED chip (e.g., light-emitting diode 9) and a display backplane (e.g., substrate 1 + conductive metal layer 2) assembly, wherein the display backplane assembly (e.g., substrate 1 + conductive metal layer 2) comprises:
A display backplane (e.g., substrate 1), the display backplane (e.g., substrate 1) having a first surface (e.g., upper surface of substrate 1), and an electrode connecting pad (e.g., conductive metal layer 2) being disposed on the first surface (e.g., upper surface of substrate 1), and
A planarization layer (e.g., planarization layer 3) stacked on the first surface (e.g., upper surface of substrate 1), wherein the planarization layer (e.g., planarization layer 3) defines an accommodating hole (e.g., through hole 5) extending in a thickness direction (e.g., vertical direction) of the planarization layer (e.g., planarization layer 3), wherein the accommodating hole (e.g., through hole 5) corresponds to the electrode connecting pad (e.g., conductive metal layer 2), the accommodating hole (e.g., through hole 5) comprises a first hole (e.g., through hole 5), wherein the first hole (e.g., through hole 5) extends through the planarization layer (e.g., planarization layer 3) in the thickness direction (e.g., vertical direction) so that the electrode connecting pad (e.g., conductive metal layer 2) is at least partially exposed relative to the planarization layer (e.g., planarization layer 3), and a bonding material (e.g., bonding metal layer 6) is filled in the first hole (e.g., through hole 5) and in contact with the electrode connecting pad (e.g., conductive metal layer 2).
The bonding material (e.g., bonding metal layer 6) is used to electrically connect an electrode of the LED chip (e.g., light-emitting diode 9) with the electrode connecting pad (e.g., conductive metal layer 2)
The LED chip (e.g., light-emitting diode 9) on the planarization layer (e.g., planarization layer 3)
The LED chip (e.g., light-emitting diode 9) is disposed over a side face of the planarization layer (e.g., planarization layer 3) away from the display backplane (e.g., substrate 1), and the LED chip (e.g., light-emitting diode 9) has the electrode, wherein the electrode corresponds to at least part of the first hole (e.g., through hole 5), the electrode is electrically connected with the electrode connecting pad (e.g., conductive metal layer 2) through the bonding material (e.g., bonding metal layer 6).
Zhang (see, e.g., fig. 1), however, fails to explicitly show numerous electrodes connecting pads and a plurality of the accommodating holes, while it also fails to show this plurality of accommodating holes comprises a second hole, wherein the second hole extends through at least a side face of the planarization layer away from the display backplane, and an adhesive is filled in the second hole, and the adhesive is used to adhere the LED chip to the planarization layer.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to duplicate the electrode connecting pads and accommodating holes of Zhang in order to the conductive connections necessary within the planarization layer, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Zhang (see, e.g., fig. 1), however, fails to show the plurality of accommodating holes comprises a second hole, wherein the second hole extends through at least a side face of the planarization layer away from the display backplane, and an adhesive is filled in the second hole, and the adhesive is used to adhere the LED chip to the planarization layer.
Gang (see, e.g., fig. 2) in a similar device to Zhang, teaches an adhesive material (e.g., adhesive layer 300), used to adhere a chip (e.g., semiconductor chip 100) to a planarization layer (e.g., flat glass pattern 600).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the adhesive material of Gang within at least some of the duplicated accommodating holes of Zhang, in order to adhere the LED chip to the other layers of the device as needed (see, e.g., paragraph 25 of Gang) via the chip’s electrode. Note that the LED chip lies on the planarization layer on the opposite side of the display backplane, and the duplicated accommodating holes (through hole 5 of Gang) extend through this side away from the display backplane.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang (CN 112652697 A) in view of Gang (US 20210066368 A1) further in view of Shohji (US 20210104571 A1).
Regarding claim 4, Zhang in view of Gang teaches the accommodating holes (e.g., duplicated through holes 5) have a space therebetween (e.g., note that conductive metal layer 2 expands outward, so duplicated accommodating holes 5 are separated by the expanding duplicated conductive metal layers 2) in the direction perpendicular to the thickness direction (e.g., vertical direction) of the planarization layer (e.g., planarization layer 3).
Zhang in view of Gang, however, fails to teach the space has a size in a radial direction of the accommodating hole that is larger than a diameter of the accommodating hole.
Shohji (see, e.g., fig. 13A), in a similar device to Zhang in view of Gang, teaches a space between wiring layers (e.g., multi-layered wiring layers 105) is larger than a diameter of the wires (see, e.g., paragraph 292 “…a through hole having a diameter smaller than that of the space between the two wiring lines…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the space separation to diameter configuration of Shohji within the accommodating hole layout of Zhang in view of Gang, in order to reduce the potential electrical coupling between the conductive structures, minimizing signal crosstalk within the device.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang (CN 112652697 A) in view of Gang (US 20210066368 A1) further in view of Song (US 20220163861 A1).
Regarding claim 11, Zhang in view of Gang fails to teach wherein a diameter of the accommodating hole at one end close to the display backplane is equal to a diameter of the accommodating hole at the other end away from a display backplane.
Song (see, e.g., fig. 1A), in a similar device to Zhang in view of Gang, teaches a conductive structure (e.g., wiring via 113) has an equal diameter on both ends (see, e.g., fig. 1A and straight/even geometry of wiring via 113) connected to an electrode (e.g., wiring electrode 115).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the straight-via geometry of Song within the through-hole conductive structure of Zhang in view of Gong, in order to achieve the expected result of reducing the cost of fabricating the structure during manufacturing, as opposed to expanding the through- hole’s conductive diameter outwards past the electrode.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang (CN 112652697 A) in view of Gang (US 20210066368 A1) further in view of Lin (US 20070023919 A1).
Regarding claim 13, Zhang (see, e.g., 30) shows most aspects of the instant invention, including a method for manufacturing a display backplane assembly, comprising:
Preparing a planarization layer (e.g., planarization layer 3) on a first surface (e.g., upper surface of substrate 1) of a display backplane (e.g., substrate 1), wherein an electrode connecting pad (e.g., conductive metal layer 2) is disposed on the first surface (e.g., upper surface of substrate 1), and
defining an accommodating hole (e.g., through hole 5) on the planarization layer (e.g., planarization layer 3) in a thickness direction (e.g., vertical direction) of the planarization layer (e.g., planarization layer 3), wherein the accommodating hole (e.g., through hole 5) corresponds to the electrode connecting pad (e.g., conductive metal layer 2), the accommodating hole (e.g., through hole 5) comprises a first hole (e.g., through hole 5), wherein the first hole (e.g., through hole 5) extends through the planarization layer (e.g., planarization layer 3) in the thickness direction (e.g., vertical direction) so that the electrode connecting pad (e.g., conductive metal layer 2) is at least partially exposed relative to the planarization layer (e.g., planarization layer 3),
The bonding material (e.g., bonding metal layer 6) in the first hole (e.g., through hole 5), wherein the bonding material (e.g., bonding metal layer 6) contacts the electrode connecting pad (e.g., conductive metal layer 2)
Zhang (see, e.g., fig. 1), however, fails to explicitly show numerous electrodes connecting pads and a plurality of the accommodating holes, while it also fails to show this plurality of accommodating holes comprises a second hole, and an adhesive is filled in the second hole, while it also fails to show filling the bonding material in the first hole.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to duplicate the electrode connecting pads and accommodating holes of Zhang in order to the conductive connections necessary within the planarization layer, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Zhang (see, e.g., fig. 1), however, fails to show this plurality of accommodating holes comprises a second hole, and an adhesive is filled in the second hole, while it also fails to show filling the bonding material in the first hole.
Gang (see, e.g., fig. 2) in a similar device to Zhang, teaches an adhesive material (e.g., adhesive layer 300), used to adhere a chip (e.g., semiconductor chip 100) to a planarization layer (e.g., flat glass pattern 600).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the adhesive material of Gang within at least some of the duplicated accommodating holes of Zhang, in order to adhere the LED chip to the other layers of the device as needed (see, e.g., paragraph 25 of Gang).
Zhang in view of Gang, however, fails to teach filling the bonding material in the first hole.
Lin (see, e.g., paragraph 34), in a similar device to Zhang in view of Gang, teaches depositing a bonding metal (e.g., bonding metal layer 20) by filling (see, e.g., paragraph 34 “The metal suited for the bonding metal layer 20 may be deposited by using electroplating, electroless, chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the filling technique of Lin to fill the through hole of Zhang in view of Gang with the bonding metal, as the filling techniques of Lin were well-known at the time of filing the invention in order to deposit a bonding metal.
Regarding claim 14, Zhang (see, e.g., fig. 1) shows transferring (see, e.g., paragraph text “…the LED chip is set on the bonding metal layer 6…”) an LED chip (e.g., light-emitting diode 9) to a side face of the planarization layer (e.g., planarization layer 3) away from the display backplane (e.g., substrate 1), wherein the LED chip (e.g., light-emitting diode 9) has an electrode (see annotated fig. 2 below), the electrode (see annotated fig. 2 below) corresponds to at least part of the first hole (e.g., through hole 5), the electrode (see annotated fig. 2 below) is electrically connected with the electrode connecting pad (e.g., conductive metal layer 2) through the bonding material (e.g., bonding metal layer 6).
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Annotated Fig. 2
Zhang in view of Gang teaches adhering the LED (e.g., light-emitting diode 9) to a planarization layer (e.g., planarization layer 3) (see paragraphs 35-36 above) via an adhesive (e.g., duplicated adhesive-filled through holes 5).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the adhesive material of Gang to adhere the LED chip and planarization layer of Zhang via the electrode, in order to achieve the expected result of reducing the amount of adhesive necessary to fix the LED chip and planarization layer together (note that the electrode is closer to the planarization layer than the LED chip is), reducing the required material and therefore cost during manufacturing.
Allowable Subject Matter
Claims 7, 9, and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814