DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11 March 2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Response to Arguments
Applicant's arguments filed 11 March 2026 have been fully considered but they are not persuasive.
Applicant states:
However, Fujiyoshi discloses a second planarization layer (452), a second barrier layer (462), a first planarization layer (51), and a first barrier layer (461).
Although Fujiyoshi discloses a stack structure similar to the claimed base layer, a critical distinction remains. To align with the limitation that the compensation electrode is positioned between BA1 and PI2, the planarization layer (81) of Fujiyoshi would have to correspond specifically to the second barrier layer (462) of Fujiyoshi.
However, the specific configuration, where the compensation electrode is disposed between and in contact with both BA1 and PI21, cannot be derived from or suggested by the combination of Lu and Fujiyoshi.
Applicant Arguments/Remarks Made in an Amendment (filed 11 March 2026) at 8. The Examiner respectfully asserts Lu in view of Fujiyoshi and Zhang discloses each of the limitations of Applicant’s currently amended independent claim 1, detailed below in the rejection of claim 1. In particular, Lu in view of Fujiyoshi and Zhang discloses a configuration wherein the second and first pixel definition layers 150/140 may be interpreted to be a first organic layer and a first barrier layer, respectively, and the planarization layer 51 and barrier layer 462 may be interpreted to be a second organic layer and a second barrier layer, respectively, and further wherein at least a portion of the first and second electrode 2 and 3 would be disposed between and in contact with the first barrier layer (pixel definition layer 140) and the second organic layer (planarization layer 51).
Accordingly, Applicant’s arguments are unpersuasive.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1-8, 11, 12, 15, and 16 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Publication No. 2022/0328611 (filed Mar. 15, 2021) (hereinafter “Lu”) in view of U.S. Patent Publication No. 2022/0293871 (filed Mar. 3, 2022) (hereinafter “Fujiyoshi”) and further in view of U.S. Patent Publication No. 2020/0219949 (filed Jan. 15, 2019) (hereinafter “Zhang”).
Regarding independent claim 1, Lu discloses: A display panel (FIG. 1b, [0060]: “FIG. 1b is a schematic view showing a first basic structure of a display substrate provided by the embodiment of the present disclosure”) comprising:
a base layer (FIGS. 1b/2/6/7/8, disclosing wherein the display substrate includes a planarization layer 81 and a pixel defining layer 80 collectively forming a base layer, [0132]) including an active area (1b/2/6/7/8, depicting wherein the planarization layer 81 and pixel defining layer 80 are formed over the entirety of the display substrate, including in the display area and the non-display area of the display substrate; [0092]: “Specifically, the display substrate can include a display area and a non-display area, wherein a plurality of repeating units are provided in the display area, each repeating unit includes a plurality of sub-pixels . . . .”) and a peripheral area disposed adjacent to the active area (FIGS. 1b/2/6/7/8, depicting wherein the planarization layer 81 and pixel defining layer 80 are formed over the entirety of the display substrate, including in the display area and the non-display area of the display substrate; [0093]: “The non-display area surrounds the display area.”), and
a compensation electrode (FIG. 1b, first electrode 2 and second electrode 3, [0090]),
the compensation electrode including:
a compensation pattern (FIG. 1b, first electrode 2, disposed in the display area, [0090]) disposed in the active area; and
a contact pattern (FIG. 1b, second electrode 3, disposed in the non-display area and electrically connected to the first electrode 2, [0090]) electrically connected to the compensation pattern and disposed in the peripheral area;
at least one transistor (FIGS. 1b/6/7/8/11a-e, driving circuit layer 85, [0100]: “Specifically, the display substrate includes a driving circuit layer, the driving circuit layer includes a plurality of pixel driving circuits, and the specific structure of the pixel driving circuit can be set according to actual needs. Exemplarily, the pixel driving circuit adopts a 7T1C circuit, which includes seven transistors and one capacitor.”) disposed on the base layer; and
a light emitting element (FIGS. 1b/4/5/6/7/8/11a-e, depicting a light emitting element comprising an anode pattern 4, organic light-emitting material layer 83, and third electrode 5, [0139], [0157]-[0158]) including:
a first electrode (FIGS. 1b/4/5/6/7/8/11a-e, anode pattern 4 electrically connected to the driving circuit layer 85, [0105]) electrically connected to the at least one transistor;
a second electrode (FIGS. 1b/4/5/6/7/8/11a-e, third electrode 5 disposed on the anode pattern 4, [0140]) disposed on the first electrode;
and a light emitting pattern (FIGS. 1b/4/5/6/7/8/11a-e, organic light-emitting material layer 83 disposed between the anode pattern 4 and the third electrode 5) disposed between the first electrode and the second electrode,
wherein the second electrode (FIGS. 1b/4/5/6/7/8/11a-e, third electrode 5) is disposed in the active area and the peripheral area (FIGS. 1b/4/5/6/7/8/11a-e, depicting wherein the third electrode 5 is disposed in both the display area and the non-display area, [0139]), and is electrically connected to the contact pattern in the peripheral area (FIGS. 6/7, depicting wherein the third electrode is electrically connected to the conductive pattern 32 and annular portion 310 of the second electrode 3).
Lu does not specifically disclose wherein the base layer includes a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer, which are sequentially stacked.
In the same field of endeavor, however, Fujiyoshi discloses a display panel (FIGS. 10/11, depicting a subpixel 411R of a display apparatus, [0081]) including a planarization layer configuration comprising a planarization layer (FIG. 11, second planarization layer 452 which is an organic layer, [0082]), a barrier layer (FIG. 11, second barrier layer 462 which is an inorganic layer, [0082]), another planarization layer (FIG. 11, first planarization layer 51 which is an organic layer, [0082]), and another barrier layer (FIG. 11, first barrier layer 461 which is an inorganic layer, [0082]), which are sequentially stacked (FIG. 11, depicting wherein the layers appear in the order they are recited). Regarding the planarization layer configuration, in [0089], Fujiyoshi states: “In this way, the display apparatus according to the present embodiment includes the second barrier layer 462 in addition to the first barrier layer 461. The relay electrode 473 fills the fourth through portion 462 h formed on the second barrier layer 462, and this can suppress the infiltration of moisture from the second planarization layer 452 to the light emitting layer 74 through the fourth through portion 462 h. As a result, even when there is a crack etc. on one of the first barrier layer 461 and the second barrier layer 462, the other barrier layer can suppress the infiltration of moisture from the second planarization layer 452 to the light emitting layer 74. This can more surely suppress the infiltration of moisture into the light emitting layer 74.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display substrate of Lu by substituting the planarization layer configuration of Fujiyoshi in order to improve the moisture barrier properties of the display substrate. See Fujiyoshi [0089].
Further, in the same field of endeavor, Zhang discloses a display panel (FIG. 4, depicting an array substrate, [0031]) including a pixel defining layer configuration comprising a first pixel defining layer (FIG. 4, first pixel defining layer 140 which is an inorganic layer, [0040]) and a second pixel defining layer (FIG. 4, second pixel defining layer 150 which is an organic layer, [0041]). Regarding the pixel defining layer configuration, in [0027], Zhang states: “[A] pixel defining layer made of an inorganic material can improve moisture barrier property of the pixel region.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display substrate of Lu by substituting the pixel defining layer configuration of Zhang in order to improve the moisture barrier properties of the display substrate. See Zhang [0027].
Moreover, the resultant configuration of both the planarization layer configuration of Fujiyoshi and the pixel defining layer configuration of Zhang is one in which the base layer (Lu FIGS. 1b/2/6/7/8, a planarization layer 81 and a pixel defining layer 80 collectively forming a base layer) includes a first organic layer (Fujiyoshi FIG. 11; Zhang FIG. 4; e.g., second pixel defining layer 150), a first barrier layer (Fujiyoshi FIG. 11; Zhang FIG. 4; e.g., first pixel defining layer 140), a second organic layer (Fujiyoshi FIG. 11; Zhang FIG. 4; e.g., first planarization layer 51), and a second barrier layer (Fujiyoshi FIG. 11; Zhang FIG. 4; e.g., second barrier layer 462), which are sequentially stacked (Fujiyoshi FIG. 11; Zhang FIG. 4; Lu FIGS. 1b/2/6/7/8, depicting wherein the layers would appear in the order they are recited), and further wherein the compensation electrode (FIG. 1b, first electrode 2 and second electrode 3, [0090]) would be disposed between the first barrier layer and the second organic layer and in contact with the first barrier layer and the second organic layer (Fujiyoshi FIG. 11; Zhang FIG. 4; Lu FIGS. 1b/2/6/7/8; depicting in, e.g., FIG. 7 wherein the first electrode 2 and second electrode 3 would be disposed between the first pixel defining layer 140 and the first planarization layer 51, and wherein at least a portion of the first electrode 2 and second electrode 3, such as, e.g., the conductive pattern 32, would be in contact with the first pixel defining layer 140 and the first planarization layer 51, and would be disposed between the first pixel defining layer 140 and the first planarization layer 51).
Regarding claim 2, Lu in view of Fujiyoshi and Zhang further discloses wherein the contact pattern (Lu FIGS. 1b/4/5/6/7, second electrode 3) surrounds the active area in a plan view (Lu FIGS. 1b/4/5/6/7, depicting wherein the second electrode 3 surrounds the display area in a plan view, [0095]).
Regarding claim 3, Lu in view of Fujiyoshi and Zhang further discloses wherein the compensation pattern (FIGS. 1b/4/5/6/7, first electrode 2) comprises first patterns (FIG. 1b, depicting wherein the first electrode 2 comprises first patterns comprising either of the horizontally extending or vertically extending portions of the first electrode 2) each extending in a first direction and spaced apart from each other in a second direction intersecting the first direction (FIG. 1b, depicting wherein both of the horizontally or vertically extending portions of the first electrode 2 extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction).
Regarding claim 4, Lu in view of Fujiyoshi and Zhang further discloses wherein the compensation pattern (FIGS. 1b/4/5/6/7, first electrode 2) further comprises second patterns (FIG. 1b, depicting wherein the first electrode 2 comprises second patterns comprising either of the horizontally extending or vertically extending portions of the first electrode 2) each extending in the second direction, intersecting the first patterns, and spaced apart from each other in the first direction (FIG. 1b, depicting wherein both of the horizontally or vertically extending portions of the first electrode 2 extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction).
Regarding claim 5, Lu in view of Fujiyoshi and Zhang further discloses wherein
an end of each of the first patterns (FIG. 1b, depicting wherein the first electrode 2 comprises first patterns comprising either of the horizontally extending or vertically extending portions of the first electrode 2, and further wherein the first patterns of the first electrode 2 have two ends) is electrically connected to a first side of the contact pattern, which extends in the second direction (FIG. 1b, depicting wherein the second electrode 3 includes a conductive pattern 32 including four sides, and further wherein, in one nonlimiting example in which the first patterns of the first electrode 2 are interpreted to be the horizontally extending portions of the first electrode 2, the conductive pattern 32 includes a first side extending vertically, and the horizontally extending portions of the first electrode 2 each include a first end electrically connected to the first side of the conductive pattern 32 extending vertically),
another end of each of the first patterns (FIG. 1b, depicting wherein the first electrode 2 comprises first patterns comprising either of the horizontally extending or vertically extending portions of the first electrode 2, and further wherein the first patterns of the first electrode 2 have two ends) is electrically connected to a second side of the contact pattern, which extends in the second direction and is spaced apart from the first side in the first direction (FIG. 1b, depicting wherein the second electrode 3 includes a conductive pattern 32 including four sides, and further wherein, in one nonlimiting example in which the first patterns of the first electrode 2 are interpreted to be the horizontally extending portions of the first electrode 2, the conductive pattern 32 includes a second side extending vertically and spaced apart from the first side extending vertically, and the horizontally extending portions of the first electrode 2 each include a second end electrically connected to the second side of the conductive pattern 32 extending vertically and spaced apart from the first side extending vertically),
an end of each of the second patterns (FIG. 1b, depicting wherein the first electrode 2 comprises second patterns comprising either of the horizontally extending or vertically extending portions of the first electrode 2, and further wherein the second patterns of the first electrode 2 have two ends) is electrically connected to a third side of the contact pattern, which extends in the first direction and is electrically connected to an end of each of the first side and the second side of the contact pattern (FIG. 1b, depicting wherein the second electrode 3 includes a conductive pattern 32 including four sides, and further wherein, in one nonlimiting example in which the second patterns of the first electrode 2 are interpreted to be the vertically extending portions of the first electrode 2, the conductive pattern 32 includes a third side extending horizontally and electrically connected to an end of each of the first and second vertically extending sides of the conductive pattern 32, and the vertically extending portions of the first electrode 2 each include a first end electrically connected to the third side of the conductive pattern 32 extending horizontally and electrically connected to an end of each of the first and second vertically extending sides of the conductive pattern 32), and
another end of each of the second patterns (FIG. 1b, depicting wherein the first electrode 2 comprises second patterns comprising either of the horizontally extending or vertically extending portions of the first electrode 2, and further wherein the second patterns of the first electrode 2 have two ends) is electrically connected to a fourth side of the contact pattern, which extends in the first direction and is electrically connected to another end of each of the first side and the second side of the contact pattern (FIG. 1b, depicting wherein the second electrode 3 includes a conductive pattern 32 including four sides, and further wherein, in one nonlimiting example in which the second patterns of the first electrode 2 are interpreted to be the vertically extending portions of the first electrode 2, the conductive pattern 32 includes a fourth side extending horizontally and electrically connected to an end of each of the first and second vertically extending sides of the conductive pattern 32, and the vertically extending portions of the first electrode 2 each include a second end electrically connected to the fourth side of the conductive pattern 32 extending horizontally and electrically connected to an end of each of the first and second vertically extending sides of the conductive pattern 32).
Regarding claim 6, Lu in view of Fujiyoshi and Zhang further discloses wherein the compensation pattern (FIGS. 1b/4/5/6/7, first electrode 2) further comprises pattern openings defined by the first patterns and the second patterns, and disposed in the active area (FIG. 1b, depicting wherein the first electrode 2 comprises first and second patterns comprising either of the horizontally extending or vertically extending portions of the first electrode 2, and further wherein the first electrode 2 includes pattern openings between the first and second patterns comprising either of the horizontally extending or vertically extending portions of the first electrode 2 disposed in the display area).
Regarding claim 7, Lu in view of Fujiyoshi and Zhang further discloses wherein the contact pattern (FIGS. 1b/4/5/6/7, second electrode 3) comprises: a main pattern surrounding the active area in a plan view (FIG. 1b, depicting wherein the second electrode 3 includes a conductive pattern 32 surrounding the display area in a plan view); and a sub pattern (FIG. 1b, fan-out area 72, [0093]) protruding from a portion of the main pattern in a direction away from the active area (FIG. 1b, depicting wherein the fan-out area 72 protrudes from the conductive pattern 32 in a direction away from the display area).
Regarding claim 8, Lu in view of Fujiyoshi and Zhang further discloses wherein a width of the sub pattern (FIG. 1b, fan-out area 72) in a direction the portion of the main pattern extends decreases along the direction the sub pattern protrudes (FIG. 1b, depicting wherein the fan-out area 72 has a width that decreases in a direction away from the display area).
Regarding claim 11, Lu in view of Fujiyoshi and Zhang further discloses wherein each of the first organic layer (Fujiyoshi FIG. 11; Zhang FIG. 4; e.g., second pixel defining layer 150) and the second organic layer (Fujiyoshi FIG. 11; Zhang FIG. 4; e.g., first planarization layer 51) comprises polyimide (Fujiyoshi FIG. 11; Zhang FIG. 4; Fujiyoshi [0040]: “The first planarization layer 51 is formed from, for example, a polyimide resin of fluorinated polyimide etc., an acrylic resin, or other organic materials.”; Zhang [0041]: “Referring to FIG. 2, the second pixel defining layer 150 is an organic layer made of acrylic, polyimide, epoxy resin, etc.,”).
Regarding claim 12, Lu in view of Fujiyoshi and Zhang further discloses wherein each of the first barrier layer (Fujiyoshi FIG. 11; Zhang FIG. 4; e.g., first pixel defining layer 140) and the second barrier layer (Fujiyoshi FIG. 11; Zhang FIG. 4; e.g., second barrier layer 462) comprises silicon oxide (Fujiyoshi FIG. 11; Zhang FIG. 4; Zhang [0040]: “Referring to FIG. 1, the first pixel defining layer 140 is an inorganic layer having a thickness of 300-500 nm, and the inorganic layer is made of silicon nitride, silicon oxynitride, silicon oxide, etc.”; Fujiyoshi [0086]: “An inorganic material film, such as silicon oxide, silicon nitride, and aluminum oxide, can be used for the second barrier layer 462.”).
Regarding claim 15, Lu in view of Fujiyoshi and Zhang further discloses wherein the display panel (FIG. 1b, [0060]: “FIG. 1b is a schematic view showing a first basic structure of a display substrate provided by the embodiment of the present disclosure”) further comprises:
a dummy electrode (FIGS. 1b/2/6/7, conductive pattern 32) directly contacting the second electrode in the peripheral area (FIGS. 1b/2/6/7, depicting wherein the conductive pattern 32 directly contacts the third electrode 5 in the non-display area),
wherein the dummy electrode and the first electrode are disposed on a same layer (FIGS. 1b/2/5/6/7, depicting wherein the conductive pattern 32 and the anode pattern 4 are on a same layer, e.g., under the pixel defining layer 80).
Regarding claim 16, Lu in view of Fujiyoshi and Zhang further discloses wherein the display panel (FIG. 1b, [0060]: “FIG. 1b is a schematic view showing a first basic structure of a display substrate provided by the embodiment of the present disclosure”) further comprises:
a first intermediate insulating layer (FIG. 8, third insulating layer ILD, [0132]) disposed on the at least one transistor (FIG. 8, disclosing wherein the third insulating layer ILD is disposed on the layers of the transistor, [0132]: “It should be noted that, as shown in FIG. 8, the manufacturing process of the display substrate may include: in a direction away from the substrate, on the substrate (which may include a first polyimide layer, a first barrier layer, and a second polyimide layer, and a second barrier layer that are stacked in sequencer) a buffer layer Buffer, a barrier layer Barrier, an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2, a third insulating layer ILD, a source-drain metal layer SD, a planarization layer 81 (PLN), an anode layer Anode, a pixel defining layer 80 (PDL) and a spacer 82 (PS) layer are sequentially formed . . . .”); and
a first connection electrode (FIG. 8, source-drain metal layer SD) disposed on the first intermediate insulating layer in the active area (FIG. 8, disclosing wherein the third insulating layer ILD is disposed on the layers of the transistor, [0132]: “It should be noted that, as shown in FIG. 8, the manufacturing process of the display substrate may include: in a direction away from the substrate, on the substrate (which may include a first polyimide layer, a first barrier layer, and a second polyimide layer, and a second barrier layer that are stacked in sequencer) a buffer layer Buffer, a barrier layer Barrier, an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2, a third insulating layer ILD, a source-drain metal layer SD, a planarization layer 81 (PLN), an anode layer Anode, a pixel defining layer 80 (PDL) and a spacer 82 (PS) layer are sequentially formed . . . .”), and electrically connected to the first electrode and the at least one transistor (FIG. 3, depicting wherein each of the transistors are electrically connected to the OLED).
Claims 13 and 14 are rejected under 35 U.S.C. § 103 as being unpatentable over Lu in view of Fujiyoshi and Zhang, and further in view of U.S. Patent Publication No. 2022/0045019 (filed Sept. 5, 2021) (hereinafter “Nakano”).
Regarding claim 13, Lu does not specifically disclose wherein the compensation electrode comprises a lower layer, an intermediate layer, and an upper layer, which are sequentially stacked, and a thickness of the intermediate layer is greater than a thickness of the lower layer and a thickness of the upper layer in a thickness direction of the base layer.
In the same field of endeavor, Nakano discloses an electrode (FIG. 3, depicting various electrodes, including a first lower electrode 14a, a source connecting electrode 12c, and a bias connecting electrode 41, [0042]), wherein the electrode comprises a lower layer, an intermediate layer, and an upper layer, which are sequentially stacked (FIG. 3, [0042]: “The first lower electrode 14 a, the source connecting electrode 12 c, and the bias connecting electrode 41 have, for example, a three-layer laminated structure in which a metal film composed of aluminum (Al) is sandwiched between two metal films composed of titanium (Ti).”), and further wherein a thickness of the intermediate layer is greater than a thickness of the lower layer and a thickness of the upper layer in a thickness direction of the base layer (FIG. 3, [0042]: “The two metal films composed of titanium (Ti) have different film thicknesses (e.g. 100 nm and 50 nm) from each other. The metal film composed of aluminum (Al) has a film thickness of, for example, 300 nm.”). Regarding the configuration of the electrodes, in [0042], Nakano states: “Since the first lower electrode 14 a and the source connecting electrode 12 c contain aluminum, the first lower electrode 14 a and the source connecting electrode 12 c have comparatively low values of resistance, as aluminum has a comparatively small value of resistance.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display substrate of Lu by substituting the compensation electrode comprising the first electrode 2 and second electrode 3 with titanium/aluminum/titanium electrode configuration of Nakano in order to decrease the resistance of the electrodes. See Nakano [0042].
Regarding claim 14, Lu in view of Nakano further discloses wherein each of the lower layer and the upper layer comprises titanium (Nakano FIG. 3, [0042]: “The first lower electrode 14 a, the source connecting electrode 12 c, and the bias connecting electrode 41 have, for example, a three-layer laminated structure in which a metal film composed of aluminum (Al) is sandwiched between two metal films composed of titanium (Ti).”), and the intermediate layer comprises aluminum (Nakano FIG. 3, [0042]: “The first lower electrode 14 a, the source connecting electrode 12 c, and the bias connecting electrode 41 have, for example, a three-layer laminated structure in which a metal film composed of aluminum (Al) is sandwiched between two metal films composed of titanium (Ti).”).
Claims 17 and 20 are rejected under 35 U.S.C. § 103 as being unpatentable over Lu in view of Fujiyoshi and Zhang, and further in view of U.S. Patent Publication No. 2019/0206979 (filed Dec. 18, 2018) (hereinafter “Han”).
Regarding claim 17, Lu in view of Fujiyoshi and Zhang does not specifically disclose wherein the display panel further comprises: a first compensation connection electrode disposed in the peripheral area, and electrically connected to the dummy electrode and the compensation electrode, wherein the first compensation connection electrode and the first connection electrode are disposed on a same layer.
In the same field of endeavor, Han discloses a display panel (FIG. 3, depicting an electroluminescent display device, [0038]) including a first compensation connection electrode (FIG. 3, first connection electrode 210 connecting a second electrode E2 to a low level voltage line 200, [0067]) disposed in a peripheral area (FIG. 3, depicting wherein the first connection electrode 210 is disposed in the contact portion CP), wherein the first compensation connection electrode is formed on a same layer as the source/drain electrodes S/D (i.e., first connection electrodes). Regarding the first connection electrode 210, in [0069], Han states: “The first connection electrode 210 is provided in the same layer as the source/drain electrodes S/D, and is formed of the same material as that of the source/drain electrodes S/D. In this case, the source/drain electrodes S/D and the first connection electrode 210 may be manufactured at the same time by the same process, to thereby improve a manufacturing convenience.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display substrate of Lu by adding the first connection electrode 210 of Han to the non-display area wiring configuration of Lu such that the first connection electrode 210 electrically connects to the second conductive pattern 32 and the annular portion 310, for instance, and is disposed in the same layer as the source-drain metal layer SD, in order to reduce the number of manufacturing steps, thereby improving manufacturing convenience. See Han [0069].
Regarding claim 20, Lu in view of Fujiyoshi and Zhang discloses wherein the at least one transistor comprises a source, a channel, a drain, and a gate overlapping the channel in a plan view (FIGS. 3/8, [0151]: “It should be noted that the driving circuit layer 85 refers to a structure shown in FIG. 3, and it may include an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a source-drain metal layer, and other structures.”).
Lu does not specifically disclose wherein the display panel further comprises a light blocking pattern overlapping the channel in a plan view and disposed on the base layer.
In the same field of endeavor, Han discloses a display panel (FIG. 3, depicting an electroluminescent display device, [0038]) including a light blocking pattern (FIG. 3, light shielding layer 110, [0038]) overlapping the channel in a plan view (FIG. 3, depicting wherein the light shielding layer 110 overlaps the active layer ACT) and disposed on the base layer (FIG. 3, depicting wherein the light shielding layer 110 is disposed on the substrate 100). Regarding the light shielding layer 110, in [0051], Han states: “The light shielding layer 110 according to one embodiment of the present disclosure is formed of a conductive material. When the light shielding layer 110 is in the floating state, the active layer ACT may be negatively influenced by the floating light shielding layer 110. In this reason, the light shielding layer 110 is connected with the source/drain electrodes S/D so that it is possible to prevent any adverse influence or effect on the active layer ACT.” In [0042], Han further states: “The light shielding layer 110 prevents light from being advanced to an active layer ACT to be explained later.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display substrate of Lu by adding the light shielding layer 110 of Han in order to block light incident on the display substrate, thereby preventing leakage current, and to prevent the active layer from experiencing any adverse influence. See Han [0042], [0051].
Claims 18 and 19 are rejected under 35 U.S.C. § 103 as being unpatentable over Lu in view of Fujiyoshi, Zhang, and Han, and further in view of U.S. Patent Publication No. 2021/0408190 (filed Nov. 15, 2018) (hereinafter “Yang”).
Regarding claim 18, Lu in view of Fujiyoshi, Zhang, and Han does not specifically disclose wherein the display panel further comprises: a second intermediate insulating layer disposed on the first intermediate insulating layer; and a second connection electrode disposed on the second intermediate insulating layer in the active area, and electrically connected to the first electrode and the first connection electrode.
In the same field of endeavor, however, Yang discloses a display panel (FIG. 4, array substrate 1000, [0103]) including a second intermediate insulating layer (FIG. 4, fourth insulating layer 420, which may be a passivation layer, [0089]) disposed on a first intermediate insulating layer (FIG. 4, third insulating layer 320, which may be an ILD layer, [0082]) and a second connection electrode (FIG. 4, second auxiliary drain electrode 430/432, [0093]) disposed on the second intermediate insulating layer (FIG. 4, depicting wherein the second auxiliary drain electrode 430/432 is disposed on the fourth insulating layer 420) in an active area (FIG. 4, depicting wherein the auxiliary drain electrode overlaps with the anode of the array substrate 1000), and electrically connected to a first electrode (FIG. 4, depicting wherein the second auxiliary drain electrode 430/432 is electrically connected to the anode 600, [0099]) and a first connection electrode (FIG. 4, depicting wherein the second auxiliary drain electrode 430/432 is electrically connected to a first drain electrode 132, [0069]). Regarding the fourth insulating layer 420, in [0089], Yang states: “For example, the fourth insulating layer 420 may be a passivation layer.” Regarding the auxiliary drain electrode 430/432, in [0116], Yang states: “The combination of the first auxiliary source-drain electrodes and the second auxiliary source-drain electrodes in this embodiment is called double SD technology. On one hand, by forming the first auxiliary source-drain electrodes and the second auxiliary source-drain electrodes in different layers so that the traces located in the peripheral region are located in different layers, the effect of narrow frame can be realized. On the other hand, the second auxiliary source-drain electrodes are electrically connected to the first auxiliary source-drain electrodes through via holes, which can reduce the resistance of the first auxiliary source-drain electrodes.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display substrate of Lu by adding the fourth insulating layer 420, which is a passivation layer, of Yang in order to insulate and protect the underlying layers of Lu, and adding the auxiliary drain electrode 430/432 of Yang such that the auxiliary drain electrode 430/432 is electrically connected to both the anode pattern 4 and source-drain metal layer of Lu, in order to reduce the resistance of underlying source/drain metal layers and to realize a display with a narrow frame as disclosed in Yang. See Yang [0089], [0116].
Regarding claim 19, Lu in view of Fujiyoshi, Zhang and Yang does not specifically disclose wherein the display panel further comprises: a second compensation connection electrode disposed in the peripheral area, and electrically connected to the dummy electrode and the first compensation connection electrode, wherein the second compensation connection electrode and the second connection electrode are disposed on a same layer.
In the same field of endeavor, Han discloses a display panel (FIG. 3, depicting an electroluminescent display device, [0038]) including a second compensation connection electrode (FIG. 3, second connection electrode 220 connecting a second electrode E2 to a low level voltage line 200, [0067]) disposed in the peripheral area (FIG. 3, depicting wherein the second connection electrode 220 is disposed in the contact portion CP), wherein the second compensation connection electrode is formed on a passivation layer 140. Regarding the second connection electrode 220, in [0070], Han discloses that formation of the second connection electrode 220 on the same layer as other layers made of the same materials contributes to an improvement in manufacturing convenience, because the second connection electrode 220 and the other layers may be manufactured at the same time by the same process.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display substrate of Lu by adding the second connection electrode 220 of Han to the non-display area wiring configuration of Lu such that the second connection electrode 220 electrically connects to the second conductive pattern 32 and first connection electrode 210, and further such that the auxiliary drain electrode 430/432 and the second connection electrode 220 are both disposed on the same layer, the fourth insulating layer (passivation layer) 420 for instance, in order to reduce the number of manufacturing steps, thereby improving manufacturing convenience as disclosed in Han. See Han [0070].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication No. 2024/0188380 (effectively filed Oct. 12, 2021) (disclosing an auxiliary line connection configuration similar to the claimed configuration).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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