Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated May 5, 2023, claims 1-20 are active in
this application.
Restriction
Restriction to one of the following inventions is required under 35
U.S.C. § 121:
I. Claims 1-9 and 15-20, drawn to a product, classified in CPC G11C 5/04 for the physical arrangement or supports for storage elements, e.g., memory modules.
II. Claims 10-14, drawn to a process of making the product, classified in CPC H01L 21/82 for Manufacture of integrated circuits characterized by the interconnection of a plurality of circuits, or of components, in a three-dimensional array.
Inventions I and II are related as process of making and product made. The inventions are
distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make other and materially different product or (2) that the product as claimed can be made by another and materially different process (M.P.E.P. § 806.05(f)). In the instant case the process as claimed can be used to make devices such as a PLA or a PLE.
Because these inventions are distinct for the reasons given above and have acquired a
separate status in the art as shown by their different classifications restriction for examination purposes as indicated is proper.
Election
During a telephonic interview on January 12, 2026, Mr. Gavin Giraud [Registration No.68402]
made a provisional election without traverse to prosecute the invention of Group 1 directed to Claims 1-9 and 15-20, drawn to a product, classified in CPC G11C 5/04 for the physical arrangement or supports for storage elements, e.g., memory modules.
Claims 10-14 are withdrawn from further consideration by the Examiner, 37 C.F.R. § 1.142(b), as being drawn to a non-elected invention.
Applicant is reminded that upon the cancellation of claims to a non-elected invention, the inventorship must be amended in compliance with 37 C.F.R. § 1.48(b) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. Any amendment of inventorship must be accompanied by a diligently-filed petition under 37 C.F.R. § 1.48(b) and by the fee required under 37 C.F.R. § 1.17(h).
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed May 5, 2023 have been considered.
Claim Objections
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rubin et al. [US Patent # 10,607,938].
With respect to claim 1, Rubin et al. disclose a semiconductor structure [fig. 1, col. 5, lines 40-45; col. 7, lines 1-10; and col. 20, lines 15-30] comprising: a top transistor [within T2]; a bottom transistor [within T1] stacked below the top transistor; a back-end-of-line (BEOL) memory device electrically coupled to and above the top transistor [“…The BEOL layer comprises an interconnect structure, which comprises multiple levels of metal lines and inter-level metal vias, to connect the integrated circuit components and devices (e.g., FinFET device) that are fabricated as part of the first and second device tiers T1 and T2…” – Col. 7, lines 1-10]; and a backside memory device [“…The backside layer BSL comprises a wafer substrate 100, a backside power distribution plane 102, and a layer of insulating material 104 encapsulating the backside power distribution plane 102.” – col. 5, lines 40-45] electrically coupled to and below the bottom transistor. It is noted that parts of the BSL and BEOL are parts of a memory device.
With respect to claim 2, Rubin et al. disclose the BEOL memory device comprises a low-voltage memory device and the backside memory device comprises a high-voltage memory device [“…backside power distribution planes are utilized to distribute positive power supply voltage, and BEOL power distribution planes are utilized to distribute negative power supply voltage… The backside layer BSL comprises a wafer substrate 100, a backside power distribution plane 102, and a layer of insulating material 104 encapsulating the backside power distribution plane 102. …The BEOL layer comprises a first level of metallization comprising a plurality of metallic structures M0 and vertical vias V0, a second level of metallization comprising a plurality of metallic structures M1 and vertical vias V1, a third level of metallization comprising a plurality of metallic structures M2 and vertical vias V2, and a fourth level of metallization comprising a plurality of metallic structures M3.” – col. 4, lines 50-55; col. 5, lines 40-45; and, col. 7, lines 10-20]. It is noted that parts of the BSL and BEOL are parts of a memory device.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for
all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was
made.
Claim 9 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Rubin et al. [US
Patent # 10,607,938] in view of Suh et al. [U.S. Patent Application # 20220216328].
Rubin et al. disclose a semiconductor structure [fig. 1, col. 5, lines 40-45; col. 7, lines 1-10; and col. 20, lines 15-30] comprising: a top transistor [within T2]; a bottom transistor [within T1] stacked below the top transistor; a back-end-of-line (BEOL) memory device electrically coupled to and above the top transistor [“…The BEOL layer comprises an interconnect structure, which comprises multiple levels of metal lines and inter-level metal vias, to connect the integrated circuit components and devices (e.g., FinFET device) that are fabricated as part of the first and second device tiers T1 and T2…” – Col. 7, lines 1-10]; and a backside memory device [“…The backside layer BSL comprises a wafer substrate 100, a backside power distribution plane 102, and a layer of insulating material 104 encapsulating the backside power distribution plane 102.” – col. 5, lines 40-45] electrically coupled to and below the bottom transistor. Additionally, Rubin et al. disclose the BEOL memory device comprises a low-voltage memory device and the backside memory device comprises a high-voltage memory device [“…backside power distribution planes are utilized to distribute positive power supply voltage, and BEOL power distribution planes are utilized to distribute negative power supply voltage… The backside layer BSL comprises a wafer substrate 100, a backside power distribution plane 102, and a layer of insulating material 104 encapsulating the backside power distribution plane 102. …The BEOL layer comprises a first level of metallization comprising a plurality of metallic structures M0 and vertical vias V0, a second level of metallization comprising a plurality of metallic structures M1 and vertical vias V1, a third level of metallization comprising a plurality of metallic structures M2 and vertical vias V2, and a fourth level of metallization comprising a plurality of metallic structures M3.” – col. 4, lines 50-55; col. 5, lines 40-45; and, col. 7, lines 10-20]. It is noted that parts of the BSL and BEOL are parts of a memory device.
Rubin et al. discloses all of the above mentioned, as well as the bottom transistor being a FinFET, but is silent about the bottom transistor comprises at least two gates separated by an unconnected source/drain. Suh et al. disclose that it is known that a FinFET consists of two gates [208a and 208c] separated by source [204 - left]/drain [204 - right]. See fig. 3g and par. 0027. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the Rubin et al. memory circuit element to include the element as taught by Suh et al., since the modification is merely a substitution of a functionally recognized equivalent element.
Allowable Subject Matter
Claims 15-20 are allowable over the prior art of records.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 3: The semiconductor structure of claim 2, wherein the low-voltage memory device comprises a dynamic random access memory (DRAM) device comprising a metal-insulator-metal (MIM) capacitor.
-with respect to claim 6: The semiconductor structure of claim 2, wherein the high voltage memory comprises a selection from the group consisting of: (i) a resistive random access memory (RRAM) device comprising a metal-insulator-metal (MIM) capacitor and at least one second bottom transistor, and (ii) a phase change memory (PCM) device comprising a MIM capacitor and at least one second bottom transistor.
-with respect to claim 15, an unconnected S/D; a second S/D electrically connected to a bottom memory device; a first gate between the first S/D and the unconnected S/D; and a second gate between the unconnected S/D and the second S/D.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 January 12, 2026
Prosecution Insights