DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is amended in a curative manner. The objection is withdrawn.
Response to Arguments
Applicant's arguments filed 3/16/2026 have been fully considered but they are not persuasive. The Applicant argues that Kim does not cure the deficiencies of Junwoo. The Examiner disagrees because the deficiencies which Kim must remedy are that of crystal structure, a sufficient motivation to combine being provided by Kim to function as a seed layer (a property which benefits from certain crystal structures). The propriety of the rejection concerning claim 1 concerning the combination of Kim thus seems to be proper. If more was required, then Kim would be a better primary reference and there would be no need for Junwoo.
The Applicant argues against the propriety of the Examiners rejection under M.P.E.P. 2144.05 II (A). The Examiner disagrees because the broadness of claim 1 allows for this rejection. The Examiner agrees that there are differences between the cited references and the as-filed specification, but these differences cannot be read into the claims. And although the claims are informed by the specification, the broadness of the phrase at issue in claim 1 allows for a rejection under M.P.E.P. 2144.05 II (A). In specific, it is determined that the person of ordinary skill in the art would have the necessary skills to arrive at the limitation at issue given the disclosure of Junwoo concerning the formation of amorphous TiO2 (crystalline and amorphous materials comprising their own benefits). Drawing a relationship between the thickness of the first interlayer and the dielectric layer, when the limitation is read according to its plain meaning, seems at least more likely than not to be the result of experimental optimization. This determination being assisted by the broadness thereof.
In addition, it would have been obvious to a person of ordinary skill in the art to modify Junwoo to meet the limitations of claim 1 concerning the thickness of the interlayer when compared to the dielectric layer to minimize the size of the structure and thus allow for a higher circuit density in the application of the structure. Indeed, Junwoo teaching the effects of the thickness would allow the person of ordinary skill in the art to understand that the structure should be minimized but that the thickness of the layers must be considered in operation i.e., the dielectric layer should be thin to minimize the size of the structure but not too thin to were the dielectric layer would affect the operating of the device. Thus, providing a reasonable expectation of success in the thickness relationship between the dielectric layer and another layer (there being no other layer in claim 1 which could interact with the dielectric layer aside from the electrodes).
The Applicant further argues that Junwoo teaches away from the limitations of claim 1. The Examiner agrees if the necessary clarifying and/or scope modifying limitations were added to the claims, but these possible limitations cannot be read into the claims. Again, it is the broadness of the limitations that allows for Junwoo to read on the claims, an amendment concerning the thickness relationship of the interlayer and the dielectric layer, as the Applicant has argued, being likely to overcome the rejection of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 6, 8, 9, 14, & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Korean Pat. Pub. No. KR 20210127589 A, which is of record, to Junwoo et al. (hereinafter “Junwoo”) in view of U.S. Pat. Pub. No. US 20150076658 A1 to Kim et al. (hereinafter “Kim”).
Regarding claim 1, Junwoo teaches a capacitor [0092] comprising:
a first thin-film electrode layer (first electrode BE; fig. 11) [0090];
a second thin-film electrode layer (second electrode UE; fig. 11) [0090];
a dielectric layer (300; fig. 11) [0018] between the first thin-film electrode layer (BE) and the second thin-film electrode layer (UE); and
a first interlayer (sacrificial layer 200; fig. 11) [0013] being at least one of between the first thin-film electrode layer (BE) and the dielectric layer (300) and between the second thin-film electrode layer (UE) and the dielectric layer (300), the first interlayer (200) including first metal oxide (material of 200, at least a rutile material, among other materials) [0013] & [0015],
wherein at least one of the first thin-film electrode layer (BE) and the second thin-film electrode layer (UE) includes second metal oxide (material of either BE or UE, hereinafter “second metal oxide”) and including non-noble metal (titanium, among other materials) [0096];
the dielectric layer (300) includes third metal oxide (material of 300) having a dielectric rutile crystal structure [0019],
the first metal oxide (material of 200), the second metal oxide (material of either BE or UE), and the third metal oxide (material of 300) have different compositions (compare [0015], [0017], & [0096]; these paragraphs reciting no overlapping compositions) from one another,
the first metal oxide (200) includes GeO2 [0015], and the third metal oxide (material of 300) includes TiO2 [0019].
Junwoo, in the embodiment of fig. 11, does not teach a thickness of the first interlayer (200) is smaller than that of the dielectric layer (300).
Junwoo, however, teaches that the thickness of the dielectric layer 300 may vary based on its formation conditions [0022] and such conditions will result in a crystalline or amorphous layer [0022]. The required general prior art conditions are thus established under M.P.E.P. 2144.05 II (A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to arrive at the thickness relationship recited in claim 1 through routine experimentation. M.P.E.P. 2144.05 II (A). In specific, it is determined that the person of ordinary skill in the art would have the necessary skills to arrive at the limitation at issue given the disclosure of Junwoo concerning the formation of amorphous TiO2 (crystalline and amorphous materials comprising their own benefits). Drawing a relationship between the thickness of the first interlayer and the dielectric layer, when the limitation is read according to its plain meaning, seems at least more likely than not to be the result of experimental optimization.
Junwoo does not teach that the second metal oxide has a rutile crystal structure.
Kim, however, teaches a capacitor (fig. 1) [0030] with electrodes (comprising a metal oxide material) [0049] which has a rutile crystal structure [0049] & [0057].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify at least one of the electrodes of Junwoo (the at least one electrode comprising the second metal oxide, as required by claim 1) to comprise a material with a rutile crystal structure to allow for at least one of the electrodes to function as a seed layer as taught by Kim [0062]-[0063].
In addition, it would have been obvious to a person of ordinary skill in the art to modify Junwoo to meet the limitations of claim 1 concerning the thickness of the interlayer when compared to the dielectric layer to minimize the size of the structure and thus allow for a higher circuit density in the application of the structure. Indeed, Junwoo teaching the effects of the thickness would allow the person of ordinary skill in the art to understand that the structure should be minimized but that the thickness of the layers must be considered in operation i.e., the dielectric layer should be thin to minimize the size of the structure but not too thin to were the dielectric layer would affect the operating of the device. Thus, providing a reasonable expectation of success in the thickness relationship between the dielectric layer and another layer (there being no other layer in claim 1 which could interact with the dielectric layer aside from the electrodes).
Regarding claim 6, Junwoo teaches the capacitor of claim 1, wherein the first interlayer (200) is a crystalline layer [0013] having a rutile crystal structure [0013] or an amorphous layer.
Regarding claim 8, Junwoo teaches the capacitor of claim 1, wherein the first interlayer (200) has a defect, and the defect includes oxygen vacancy [0023].
Regarding claim 9, Junwoo teaches the capacitor of claim 1, wherein the first metal oxide (material of 200) further comprises at least one selected from SnO2 [0015], MnO2 [0015], GeO2-a (1<a<2), SnO2-a (1<a<2), and MnO2-a (1<a<2).
Regarding claim 14, Junwoo teaches the capacitor of claim 1, wherein at least one of the first thin-film electrode layer (BE) and the second thin-film electrode layer (UE) that is not in contact with the first interlayer (200) (at least UE does not contact the layer 200) comprises at least one selected from metal, oxide of the metal, doped oxide of the metal, nitride of the metal [0096], and carbide of the metal, the metal comprises at least one selected from Ti [0096], W, Ta, Co, Mo, Ni, V, Hf, Al, Cu, Pt, Pd, Ir, Au, and Ru, the oxide of the metal comprises at least one selected from MoO2, VO2, RuO2,IrO2, PtO2, MnO2, Sb2O3,In2O3, the doped oxide of the metal comprises at least one selected from Ta-doped SnO2, Sb-doped SnO2, Ni-doped SnO2, Ti-doped In2O3, and Al-doped ZnO, and the nitride of the metal comprises at least one selected from TiN [0096], WN, VN, MoN, TaN, TiAlN, TaSiN, TiSiN, WSiN, TiCN, TiA1CN, RuCN, and RuTiN. The Office notes that the electrode UE is taught as comprising the same materials as the electrode BE in [0097].
Regarding claim 15, Junwoo teaches an electronic device comprising: a transistor (transistor) [0091]; and the capacitor of claim 1 electrically connected [0091] to the transistor (transistor).
Claims 2-5, 16, & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Junwoo in view of Kim as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20200105633 A1 to Lee et al. (hereinafter “Lee”).
Regarding claim 2, Junwoo in view of Kim does not teach the capacitor of claim 1, wherein the capacitor comprises multiple first thin-film electrode layers that are spaced apart or multiple second thin-film electrode layers that are spaced apart, the capacitor further comprises a bridge connecting the multiple first thin- film electrode layers to each other or connecting the multiple second thin-film electrode layers to each other, the first interlayer is on the bridge.
Lee, however, teaches wherein the capacitor (512; fig. 18B) comprises multiple first thin-film electrode layers (lower electrodes 501; fig. 18B) [0193] that are spaced apart (horizontally) or multiple second thin-film electrode layers that are spaced apart, the capacitor (512) further comprises a bridge (supporter 505; fig. 18B) [0195] connecting the multiple first thin-film electrode layers (501) to each other or connecting the multiple second thin-film electrode layers to each other, the first interlayer (dielectric layer 502; fig. 18B) [0193] is on the bridge (505).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the capacitor of Junwoo in view of Kim to comprise multiple thin-film electrodes (first or second type) connected by a bridge to provide lateral support to the electrodes as taught by Lee [0195].
It further would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the capacitor of Junwoo in view of Kim to extend the first interlayer to be disposed on the bridge to prevent leakage and simplify formation as taught by Lee [0198].
Regarding claim 3, Junwoo in view of Kim and Lee, as presently modified, does not teach the capacitor of claim 2, wherein the first interlayer extends from at least one of the multiple first thin-film electrode layers to another adjacent one of the multiple first thin-film electrode layers through the bridge or from at least one of the multiple second thin-film electrode layers to another adjacent one of the multiple second thin-film electrode layers through the bridge, and the first interlayer is dielectric.
Lee, however, teaches a capacitor (512; fig. 18B) wherein the first interlayer (dielectric layer 502; fig. 18B) [0198] extends from at least one of the multiple first thin-film electrode layers (second to furthest left lower electrodes 501; fig. 18B) [0193] to another adjacent one of the multiple first thin-film electrode layers (second to furthest right lower electrode 501; fig. 18B) through the bridge (505) or from at least one of the multiple second thin-film electrode layers to another adjacent one of the multiple second thin-film electrode layers through the bridge, and the first interlayer (502) is dielectric [0198].
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the capacitor of Junwoo in view of Kim and Lee to extend the first interlayer across the bridge to be disposed adjacent electrode to prevent leakage as taught by Lee [0198].
Regarding claim 4, Junwoo in view of Kim does not teach the capacitor of claim 1, wherein the thickness of the first interlayer is smaller than at least one of that of the first thin-film electrode layer and that of the second thin-film electrode layer.
Lee, however, teaches that the thickness of the first interlayer (205 fig. 18B) is considered as a balance between leakage current prevention (necessitating a thicker layer) and layer formation characteristics i.e., formation of a crystalline or amorphous dielectric [0021]. In other words, Lee teaches that there is an optimal range of thickness to balance these constraints. The prior art conditions are thus established under M.P.E.P. 2144.05 II (A).
It thus would have been obvious to a person of ordinary skill in the art to arrive at the thickness relationship recited in claim 4 as a matter of routine optimization i.e., finding the thickness which balances the constraints described by Lee. M.P.E.P. 2144.05 II (A).
Regarding claim 5, Junwoo in view of Kim does not teach the capacitor of claim 1, wherein the thickness of the first interlayer is about 1 Å or more to about less than 20 Å.
Lee, however, teaches that the thickness of the first interlayer (205; fig. 18B) is considered a balance between leakage current prevention (necessitating a thicker layer) and layer formation characteristics i.e., formation of a crystalline or amorphous dielectric [0021]. In other words, Lee teaches that there is an optimal range of thickness to balance these constraints. The prior art conditions are thus established under M.P.E.P. 2144.05 II (A).
It thus would have been obvious to a person of ordinary skill in the art to arrive at the thickness relationship recited in claim 4 as a matter of routine optimization i.e., finding the thickness which balances the constraints described by Lee. M.P.E.P. 2144.05 II (A).
Regarding claim 16, Junwoo in view of Kim does not teach the electronic device of claim 15, wherein the transistor comprises: a semiconductor substrate comprising a source region, a drain region, and a channel region being between the source region and the drain region; and a gate stack being on the semiconductor substrate, facing the channel region, and comprising a gate insulating layer and a gate electrode.
Lee, however, teaches wherein the transistor (cell transistor) comprises: a semiconductor substrate (401; fig. 17C) [0184] comprising a source region (411 left; fig. 17C) [0186], a drain region (411 right; fig. 17C) [0186], and a channel region (region of bit line contact hole 412; fig. 17C) [0187] being between the source region (411 left) and the drain region (411 right); and a gate stack (406; fig. 17C) [0185] being on the semiconductor substrate (401), facing the channel region (412), and comprising a gate insulating layer (407; fig. 17C) [0185] and a gate electrode (buried word line 408; fig. 17C) [0182].
It would have been obvious to aperson of ordinary skill in the art before the effective filing date of the invention, to modify the transistor of Junwoo to comprise the limitations of claim 16 to allow for the transistor to form a memory device when coupled with the capacitor as taught by Lee [0182].
Regarding claim 17, Junwoo in view of Kim does not teach the electronic device of claim 15, wherein the transistor comprises: a semiconductor substrate comprising a source region, a drain region, and a channel region being between the source region and the drain region; and a gate stack being in a trench inserted at a depth from a surface of the semiconductor substrate, facing the channel region, and comprising a gate insulating layer and a gate electrode.
Lee, however, teaches wherein the transistor (cell transistor) comprises: a semiconductor substrate (401; fig. 17C) [0184] comprising a source region (411 left; fig. 17C) [0186], a drain region (411 right; fig. 17C) [0186], and a channel region (region of bit line contact hole 412; fig. 17C) [0187] being between the source region (411 left) and the drain region (411 right); and a gate stack (406; fig. 17C) [0185] being in a trench (recessed portion of 406) inserted at a depth (depth of 406) from a surface of the semiconductor substrate (401), facing the channel region (412), and comprising a gate insulating layer (407; fig. 17C) and a gate electrode (buried word line 408; fig. 17C) [0182].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the transistor of Junwoo to comprise the limitations of claim 17 to allow for the transistor to form a memory device when coupled with the capacitor as taught by Lee [0182].
Claims 7, 10, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Junwoo in view of Kim as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20160133691 A1 to Phatak et al. (hereinafter “Phatak”).
Regarding claim 7, Junwoo in view of Kim does not teach the capacitor of claim 1, wherein chemical potential of the first metal oxide is higher than that of the second metal oxide and that of the third metal oxide, and chemical potential of the second metal oxide is higher than that of the third metal oxide.
Phatak, however, teaches a capacitor (fig. 1) [0014] with molybdenum oxide electrodes [0047] (molybdenum oxide having a chemical potential which is greater than TiO2 and less than GeO2; these materials being required for the third and first metal oxides as recited in claim 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the electrodes of Junwoo in view of Kim to comprise molybdenum oxide to increase work function values as taught by Phatak [0047].
Regarding claim 10, Junwoo in view of Kim does not teach the capacitor of claim 1, wherein the second metal oxide (second metal oxide) comprises at least one selected from MoO2, SnO2, Sn1-xTaxO2 (0.01≤x≤0.1), Sn1-xSbxO2 (0.01≤x≤0.1), Sn1-xSbxO2 (0.01≤x≤0.1), Sn1-xMnxO2 (0.01≤x≤0.1), and Sn1-xFexO2 (0.01≤x≤0.1).
Phatak, however, teaches a capacitor (fig. 1) [0014] with molybdenum oxide electrodes [0047].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the electrodes of Junwoo in view of Kim to comprise molybdenum oxide to increase work function values as taught by Phatak [0047].
Regarding claim 13, Junwoo in view of Kim does not teach the capacitor of claim 1, wherein at least one of the first thin-film electrode layer and the second thin-film electrode layer has a multi-layer structure, and the capacitor further comprises a second interlayer between multiple sub-electrodes that constitute at least one of the first thin-film electrode layer and second thin-film electrode layer.
Phatak, however, teaches a capacitor (fig. 1) wherein at least one of the first thin-film electrode layer (110; fig. 1) [0060] and the second thin-film electrode layer (102; fig. 1) [0053] has a multi-layer structure [0060]-[0061], and the capacitor further comprises a second interlayer (metal oxide as part of the multiple layers; fig. 1) [0061] between multiple sub-electrodes (current conductor layers as part of the multiple layers; fig. 1) [0061] that constitute at least one of the first thin-film electrode layer (110) and second thin-film electrode layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify at least one of the first and second electrode layers of Junwoo in view of Kim to comprise multiple layers of interlayers and electrodes to modify the work function of the electrode as taught by Phatak [0060]-[0061].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Junwoo in view of Kim as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20150087130 A1 to Chen et al. (hereinafter “Chen”).
Regarding claim 11, Junwoo in view of Kim teaches the capacitor of claim 1, wherein the third metal oxide (material of 300) comprises at least one selected from Ti1-yGayO2 (0.01≤y≤0.1), Ti1-yAlyO2 (0.01≤y≤0.1), Ti1-yLayO2 (0.01≤y≤0.1), Ti1-yByO2 (0.01≤y≤0.1), Ti1-yInyO2 (0.01≤y≤0.1), Ti1-yScyO2 (0.01≤y≤0.1), and Ti1-yYyO2 (0.01≤y≤0.1).
Chen, however, teaches the use of various dopants in rutile phase titanium oxide [0049]] including Ti1-yAlyO2 (0.01≤y≤0.1) [0053].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the dielectric material (comprising a third metal oxide of rutile phase titanium oxide) to comprise one of the compositions of claim 11 to modify the dielectric constant of the dielectric layer, resulting in higher electrical holding capacity for the end device as taught by Chen [0004] & [0034].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Junwoo in view of Kim as applied to claim 1 above, and further in view of Electrode thickness design toward bulk energy storage devices with high areal/volumetric energy density to Wang et al. (hereinafter “Wang”).
Regarding claim 12, Junwoo teaches the capacitor of claim 1, wherein a first thickness of the dielectric layer (300) is in a range of about 2 nm to about 100 nm [0022], and
Junwoo does not teach a second thickness of each of the first thin-film electrode layer and the second thin-film electrode layer is in a range of about 10 nm to about 1,000 nm.
Wang, however, teaches that energy density of the resulting device may be modified through electrode thickness modification (conclusion). The prior art conditions are thus established under M.P.E.P. 2144.05 II (A). It thus would have been obvious to a person of ordinary skill in the art to arrive at the limitations of claim 12 through routine experimentation. M.P.E.P. 2144.05 II (A). In specific, it is determined that the person of ordinary skill in the art would have the necessary skills to arrive at the limitation at issue given the disclosure of Junwoo concerning the formation of amorphous TiO2 (crystalline and amorphous materials comprising their own benefits). Drawing a relationship between the thickness of the first interlayer and the dielectric layer, when the limitation is read according to its plain meaning, seems at least more likely than not to be the result of experimental optimization.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Junwoo in view of Kim as applied to claim 15 above, and further in view of U.S. Pat. Pub. No. US 20200350322 A1 to Liu et al. (hereinafter “Liu”).
Regarding claim 18, Junwoo does not teach the electronic device of claim 15, further comprising: a memory cell comprising the capacitor and the transistor; and a processor electrically connected to the memory unit cell and configured to control the memory cell.
Liu, however, teaches an electronic device (300; fig. 3A) [0057] comprising a memory cell (DRAM cell 314; fig. 3A) [0055] comprising the capacitor (320; fig. 3A) [0057] and the transistor (318; fig. 3A) [0057]; and a processor (312; fig. 3A) [0057] electrically connected to the memory unit cell (314) and configured to control [0057] the memory cell (314).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the device of Junwoo to electrically connect a processor to the memory cell to allow for instant-on features in a finished device as taught by Liu [0039].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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