DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species I in Figs. 2A-2B, 2A-3B, 4A-4B in the reply filed on 6/17/2026 is acknowledged.
Claims 3-5 and 16 are drawn to Fig. 6, 7A-7B, which is non-elected embodiment, and are thus withdrawn from further consideration. Claim 6 is drawn to Fig. 5A, which is non-elected embodiment, and is thus withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites “a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate on the active fin and extending in the first direction, wherein the source/drain regions are connected to the plurality of channel layers” in lines 2-3. There is only one direction that is perpendicular to an upper surface of the substrate, which is the vertical direction that is normal to the plane of the substrate (“normal” here is used in the sense of “normal vector to a plane” as is well-known in mathematics). It is unclear how the plurality of channel layers can be spaced apart from each other in this vertical direction. Also, it is unclear whether this direction is the same or different than the first direction which is defined in claim 1 to be the fin length direction. For the purpose of examination, it is interpreted to be the same direction as the first direction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7-15, 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frougier et al. (US 2020/0044069 A1).
Regarding claim 1, Frougier teaches a semiconductor device (device in Figs. 11A-11B of Frougier), comprising:
an active fin (208) extending in a first direction (left-right direction in Fig. 11A of Frougier) on an upper surface (top surface of substrate 204) of a substrate (204), the active fin comprising a first fin portion (upper portion 206; this is best shown in Fig. 6B of Frougier) and a second fin portion (208) on the first fin portion;
an isolation pattern (203-234) between the first fin portion and the second fin portion;
a gate structure (213-214-233) intersecting the active fin and extending in a second direction (in-out direction in Fig. 11A) intersecting the first direction; and
source/drain regions (212) in regions of the second fin portion on both sides of the gate structure, respectively;
wherein the gate structure includes a gate electrode (213) intersecting a region of the active fin and extending in the second direction, a pair of gate spacers (233) extending in the second direction along both side surfaces of the gate electrode in the first direction (as shown in Fig. 11A), the pair of gate spacers and the isolation pattern comprising a same material (234 and spacer 233 are made of the same material, as described in [0045] of Frougier), and a gate insulating layer (high-k gate dielectric layer in [0082] of Frougier) between the gate electrode and the active fin.
Regarding claim 2, Frougier teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the isolation pattern includes a first portion (234) grown from an upper surface of the first fin portion (the limitation “grown from an upper surface…” is a product-by-process language which does not require the first portion to be made by the same process as along as it meets all structural limitations), and a second portion (the punch through stopper 203) having a boundary surface (interface of 203 and 234) with the first portion and grown from a lower surface of the second fin portion (the limitation “grown from a lower surface…” is a product-by-process language which does not require the second portion to be made by the same process as along as it meets all structural limitations).
Regarding claim 7, Frougier teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the isolation pattern has a width greater than a width of adjacent portions of the first and second fin portions in a cross-section of a portion of the active fin, taken in the second direction, in which the gate structure is disposed (as shown in Fig. 12B of Frougier, the width of layer 234 is greater than that of the fin’s width).
Regarding claim 8, Frougier teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the gate electrode has an extension electrode portion (portion of gate electrode 213 at the level of the layer 234. This gate electrode 213 is in place of the dummy gate electrode 231, which is shown in Fig. 5B) passing through a region (region at the level of isolation layer 234) between the first fin portion and the second fin portion to at least partially surround the second fin portion in the second direction (as shown in Fig. 5B of Frougier), and wherein the isolation pattern is divided into a first pattern and a second pattern by the extension electrode portion (as shown in Fig. 5B, the boundary of 234 and 203 is at the same level of the bottom surface of the gate, which is the same level of the gate 213).
Regarding claim 9, Frougier teaches all limitations of the semiconductor device of claim 8, and also teaches wherein the gate insulating layer has an extended portion (portion of high-k dielectric layer at the level of 234) at least partially surrounding the extension electrode portion in the first direction.
Regarding claim 10, Frougier teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the active fin includes a plurality of active fins, and the source/drain region is disposed throughout the plurality of active fins (as shown in Fig. 11A-B of Frougier), and wherein the isolation patterns of the plurality of active fins are on a same level relative to the upper surface of the substrate being a base reference level (as shown in Fig. 11B of Frougier).
Regarding claim 11, Frougier teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the isolation pattern has a sidewall extension portion extending to a sidewall of the active fin in a cross-section of a portion of the active fin, taken in the second direction, in which the source/drain regions are disposed (as shown in Fig. 12B of Frougier).
Regarding claim 12, Frougier teaches all limitations of the semiconductor device of claim 1, and further comprising: a plurality of channel layers (211 in Fig. 11A of Frougier) spaced apart from each other in a direction perpendicular to an upper surface of the substrate on the active fin and extending in the first direction (please see interpretation in 112b rejection above), wherein the source/drain regions are connected to the plurality of channel layers (as shown in Figs. 11A of Frougier), respectively, and wherein the gate electrode at least partially surrounds the plurality of channel layers and extends in the second direction (as shown in Fig. 11A of Frougier), and the gate insulating layer (high-k gate dielectric layer in [0082] of Frougier) is between the plurality of channel layers and the gate electrode and between the active fin and the gate electrode (as taught in claim 1 above).
Regarding claim 13, Frougier teaches a semiconductor device (device in Figs. 11A-11B of Frougier), comprising:
a substrate (204) having an upper surface (top surface of substrate 204) including a first region (region of the left transistor in region 201) and a second region (region of the right transistor in region 201);
a first transistor (left transistor in region 201) on the first region of the substrate; and
a second transistor (right transistor in region 201) on the second region of the substrate,
wherein the first transistor includes a first active fin (left fin 210 in Fig. 11A. The fin is labeled as shown in Fig. 3C of Frougier) extending in a first direction (left-right direction in Fig. 11A) on the first region of the substrate, the first active fin having a first fin portion (208, as shown in Fig. 3C) and a second fin portion (upper portion 206) on the first fin portion, a first isolation pattern (203-234) between the first fin portion and the second fin portion, a first gate structure (213-214-233 over the left fin in region 201) intersecting the first active fin and extending in a second direction (in-out of the page direction in Fig. 11A) intersecting the first direction, the first gate structure including a pair of first gate spacers (233) including a same material as a material of the first isolation pattern (234 and spacer 233 are made of the same material, as described in [0045] of Frougier), and first source/drain regions (212 in Fig. 11A) in regions of the second fin portion on both sides of the first gate structure, respectively, and
wherein the second transistor includes a second active fin (right fin 211) extending in the first direction on the second region of the substrate, a second gate structure (213-214-233 over the right fin in region 201) intersecting the second active fin and extending in the second direction, and second source/drain regions (source/drain region 212 between the two fins 211 in Fig. 11A) in regions of the second active fin on both sides of the second gate structure, respectively.
Regarding claim 14, Frougier teaches all limitations of the semiconductor device of claim 13, and also teaches wherein an upper end (top surface of left fin 211) of the first active fin at least partially covered by the first gate structure has a same level as a level of an upper end (top surface of right fin 211) of the second active fin at least partially covered by the second gate structure relative to the upper surface of the substrate being a base reference level (as shown in Fig. 11A of Frougier).
Regarding claim 15, Frougier teaches all limitations of the semiconductor device of claim 13, and also teaches wherein the first isolation pattern includes a first portion (203) grown (the limitation “grown from an upper surface…” is a product-by-process language which does not require the first portion to be made by the same process as along as it meets all structural limitations) from an upper surface (top surface of portion 208) of the first fin portion, and a second portion (234) having a boundary surface (as shown in Fig. 11A of Frougier) with the first portion and grown from a lower surface (bottom surface of fin portion 206) of the second fin portion.
Regarding claim 17, Frougier teaches all limitations of the semiconductor device of claim 13, and also teaches wherein the first gate structure is configured to extend to a region between the first fin portion and the second fin portion and to at least partially surround the second fin portion in the second direction (as shown in Fig. 11B of Frougier).
Regarding claim 18, Frougier teaches all limitations of the semiconductor device of claim 17, and also teaches wherein the upper surface of the substrate further includes a third region in which a third transistor is disposed, wherein the third transistor includes a third active fin extending in a first direction on the third region of the substrate, where the third active fin has a third fin portion and a fourth fin portion disposed on the third fin portion, a second isolation pattern between the third fin portion and the fourth fin portion, a third gate structure intersecting the third active fin and extending in the second direction, and third source/drain regions in regions of the third fin portion on both sides of the third gate structure, respectively, and wherein the second isolation pattern is on a same level as a level of the first isolation pattern relative to the upper surface of the substrate being a base reference level (it is implicit that the device of Frougier has many finFET transistors of the same structure as those in region 201 of Fig. 11A).
Regarding claim 19, Frougier teaches a semiconductor device (device in Figs. 11A-11B of Frougier), comprising:
an active fin (210 in Figs. 3C) disposed on a substrate (204) and extending in a first direction (fin length direction, which is left-right direction in Fig. 11A), the active fin having a first fin portion (208) and a second fin portion (206) on the first fin portion;
an isolation pattern (203-234) between the first fin portion and the second fin portion;
a gate structure (213-214-233) intersecting the active fin and extending in a second direction (in-out of the page in Fig. 11A) intersecting the first direction; and
source/drain regions (212) in regions of the second fin portion on both sides of the gate structure, respectively,
wherein the gate structure includes:
a gate electrode (213) intersecting one region of the active fin, and including an extension electrode portion (portion of gate electrode 213 at the level of the layer 234. This gate electrode 213 is in place of the gate electrode 231 in Fig. 5B) passing through the one region between the first and second fin portions to at least partially surround the second fin portion in the second direction (as shown in Fig. 5B);
a pair of gate spacers (233) extending in the second direction along both side surfaces of the gate electrode in the first direction and including a same material as a material of the isolation pattern (234 and spacer 233 are made of the same material, as described in [0045] of Frougier); and
a gate insulating film (high-k gate dielectric layer in [0082] of Frougier) between the gate electrode and the active fin.
Regarding claim 20, Frougier teaches all limitations of the semiconductor device of claim 19, and also teaches wherein the isolation pattern includes a first portion (203) grown (the limitation “grown from an upper surface…” is a product-by-process language which does not require the first portion to be made by the same process as along as it meets all structural limitations. As written, it is only required that the layer 203 is connected to the fin portion 208) from an upper surface (top surface of 208) of the first fin portion, and a second portion (234) having a boundary surface (interface of 203 and 234) with the first portion and grown from a lower surface (bottom surface of 206) of the second fin portion.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Tuan A Hoang/ Primary Examiner, Art Unit 2898
Prosecution Insights