DETAILED ACTION
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-12, 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US20210226114 A1 by Holmes et al (Holmes).
Referring to claim 1, Holmes Fig 1A -12B teaches An electronics device (Fig 1A, 12B item 100 paragraph [0067], [0068]), comprising:
a substrate (item 108);
a first layer (item 102) of a first layered material arranged over the substrate (item 108);
a second layer (item 104) of a second layered material arranged over the substrate (item 108);
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an overlap region (see Fig 1A where 104 is over 102 certain area is overlapped between them with separation layer 106);
wherein, in the overlap region(see Fig 1 A), the second layer (item 104)is arranged over the first layer (item 102), and a section of a bottom surface of the second layer is parallel to a section of a top surface of the first layer (See Fig 1A item 104 is parallel to item 102 );
a contact layer (item 106 is the contact layer) arranged over the first layer (item 102) and the second layer (item 104), wherein the contact layer comprises: a plurality of electrically conductive lines (item 114, 116 and paragraph [0097] where conducting lines are disclosed) comprising a first electrically conductive line (item 114) and a second electrically conductive line (item 116), wherein the first electrically conductive line and/or the second electrically conductive line comprises a superconductor material (See paragraph [0097]); and
an electrical insulation element (item 110) arranged between the electrically conductive lines(items 114, 116) to electrically insulate them from each other (See paragraph [0068]);
a first electrical contact (interface between the 114, 102) between the first electrically conductive line and the first layer; and
a second electrical contact (interface between 116 and 104) between the second electrically conductive line and the second layer (see paragraphs [0069] [0069] [0070]).
Referring to claim 3 Holmes teaches the electronics device according to claim 1, wherein the first layered material (Fig 1A item 102) comprises a second superconductor material (See the contact layer is a superconducting layer paragraph [0077]), and/or the second layered material (item 104) comprises a third superconductor material. (See contact layer is a superconducting layer paragraph [0077]).
Referring to claim 4 Holmes teaches the electronics device according to claim 1, but silent on wherein in the overlap region, the first layer and the second layer are in direct physical contact with each other, or spaced apart from each other by no more than 5 nm. (See paragraph [0072] where Holmes teaches the thickness of layer 106 is between 0.5 nm to 300 nm means it separates the layer 102, and layer 104 within the range of 5nm thickness).
Referring to claim 5 Holmes teaches the electronics device according to claim 1, wherein the electrical insulation element comprises silicon nitride and/or at least one metal oxide (See paragraph [0060] [0061] where Holmes teaches the insulating layers are Al-oxide layers).
Referring to claim 6 Holmes teaches the electronics device according to claim 1, wherein the first layered material and/or the second layered material comprise(s) covalently bound atomic layers, wherein a covalently bound atomic layer of the covalently bound atomic layers comprises: a nearest-neighbor atomic distance between nearest-neighbor atoms of the covalently bound atomic layer; and an interlayer distance between the covalently bound atomic layer and a covalently bound atomic layer neighboring the covalently bound atomic layer; and wherein the interlayer distance exceeds the nearest-neighbor atomic distance. (It is an inherent teaching as per CMOS technology see paragraphs [0060] and [0061] where Holmes teaches CMOS technology Si based Josephson Junction and barriers all are under semiconducting bonding structures means it follows the covalent bonding).
Referring to claim 7 Holmes teaches the electronics device according to claim 1, wherein a first section of a covalently bound atomic layer of the first layered material is parallel to a second section of a covalently bound atomic layer of the second layered material. (It is an inherent teaching as per CMOS technology see paragraphs [0060] and [0061] where Holmes teaches CMOS technology Si based Josephson Junction and barriers all are under semiconducting bonding structures means it follows the covalent bonding).
Referring to claim 8 Holmes teaches the electronics device according to claim l, wherein a crystallographic layer of the first layered material is parallel to a crystallographic layer of the second layered material. ( According to paragraphs [0061] it is crystal growth and hence it is inherent teaching).
Referring to claim 9 Holmes teaches the electronics device according to claim 1, wherein a lateral extension of the contact layer (Fig 1A, 12A item 106) fully covers a lateral extension of the overlap region (See Fig 1A, 1B or 12A, 12B see paragraph 0072]).
Referring to claim 10 Holmes teaches the electronics device according to claim 1, further comprising an encapsulation of the overlap region, wherein the encapsulation comprises at least a section of the contact layer (see Fig 1 item 106, 114 or 116 are the contact layers and encapsulation is an device packaging technique an inherent component of any semiconductor electronics devices).
Referring to claim 11 Holmes teaches the electronics device according to claim 1, wherein crystallographic orientations of the first layered material (Fig 1A item 102) and the second layered material (item 104) differ in the overlap region. (According to paragraphs [0061] layers are epitaxial crystals and item 106 separates them and hence their orientation is different over the overlap region which is inherent).
Referring to claim 12 Holmes teaches the electronics device according to claim11, further comprising: a first crystallographic orientation arranged parallel to a first crystallographic layer of the first layered material in the overlap region, and a second crystallographic orientation arranged parallel to a second crystallographic layer of the second layered material in the overlap region; wherein the differing crystallographic orientations refer to the first crystallographic orientation and the second crystallographic orientation. (See Fig 1A substrate 108 and contact layers 110 and 112 are layered epitaxial or crystal oriented structured and paragraphs [0060], [0061], [0072] where Holmes teaches crystallographic orientation and particular CMOS and SIS technologies. Hence, it is inherent teaching).
Referring to claim 14 Holmes teaches the electronics device according to claim1, further comprising a contact region in which the first layer is arranged over the substrate, wherein the second layer does not extend into the contact region, and wherein the first electrical contact is arranged in the contact region (See Fig 1A and layers 110, 112 and substrate 108 and first layer 102 and second layer 104 where 104 does not extent in to the contact region and hence it is an inherent teaching).
Referring to claim 15 Holmes teaches a method for fabricating an electronics device (See Fig 1A, 12A and paragraphs [0066] [0067]), comprising:
providing a substrate (item 108);
providing a first layer (item 102) of a first layered material over the substrate (item 108 paragraph [0067]);
providing a contact layer (item 110) separate from the first layer(item 102), wherein the contact layer comprises: a plurality of electrically conductive lines (item 114 and 116) comprising a first electrically conductive line( paragraph [0067] [0068]) ; and
an electrical insulation (item 110) element arranged between the electrically conductive lines (item 114, 116) to electrically insulate them from each other (see paragraph [0068]);
cooling the first layer (item 102) to a temperature below a first temperature of 0*C (see paragraph [0070]); and
arranging the contact layer (item 110) over the first layer (item 102), such that a first electrical contact (conducting region between 102/114) is formed (See Fig 1A/12A and paragraphs [0067]) between the first electrically conductive line (item 114 ) and the first layer (item 102).
Referring to claim 16 Holmes teaches the method according to claim 15, further comprising keeping the first layer (Fig 1A item 102) at a temperature below the first temperature while arranging the contact layer over the first layer. (See Fig 4 and [0082] where Holmes teaches first layer deposition on contact the contact layer 402 deposition using MBE technique).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 13, are rejected under 35 U.S.C. 103 as being unpatentable over Holmes reference
Referring to claim 2 Holmes teaches the electronics device according to claim 1, Holmes teacher further it comprising a first gap (item 106 defined between 102 and 104 layers paragraph [0066]) and the first layer (item 102) and/or the second layer (item 104) , and but silent on wherein the first gap (item 106) extends along at least a section of a boundary of the overlap region .However, it is within the scope of a person with ordinary skill in the art.
Referring to claim 13 Holmes teaches the electronics device according to claim l, but silent on wherein a layer of an elastomer is disposed over the contact layer. Elastomer is a polymer protection layer in device technology. Hence, it is within the scope of a person with ordinary skill in the art.
Conclusion
Claims 1-16 are rejected.
The prior of art made of record and not relied upon is considered to pertinent to applicant’s disclosure.
Applicants are directed to consider additional pertinent prior art included on the notice of references cited PTOL 892 attached here with. The examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicants. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim other passages and figures may apply. Applicant, in preparing the response should consider fully the entire reference as potentially teaching all or part of the claimed invention as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SRINIVAS SATHIRAJU whose telephone number is (571)272-4250. The examiner can normally be reached 8:30AM-3:30PM, 5PM -8:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALEXANDER H TANINGCO can be reached at 5712728048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SRINIVAS SATHIRAJU/06/03/2026
SRINIVAS . SATHIRAJU
Primary Examiner
Art Unit 2845
Prosecution Insights