DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (Kim, US 2020/0126927).
Regarding claim 1, Kim shows a semiconductor device, comprising: a plurality of chip regions ( chip region 120/110 as show in FIG. 4) on a substrate (substrate 10); at least one scribe lane (SL in FIG. 4) surrounding each of the plurality of chip regions (chip region 120/110) on the substrate (substrate 10); a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions (see FIG. 4 with respect to FIG. 9 and related text); and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane (see FIG. 4 with respect to FIG. 8-9).
Regarding claim 2, Kim shows a semiconductor device, comprising, wherein a subset of chip regions of the plurality of chip regions are included in a shot group, the shot group having an area covered by a single exposure in a photolithography process; (the underlined limitations considered as product by process) and the plurality of first align key patterns and the plurality of first test element group patterns are included in each of the chip regions of the shot group (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 3, Kim shows a semiconductor device, comprising, wherein each of the plurality of first align key patterns included in each of the chip regions of the shot group include a plurality of align key patterns used in different exposure processes; and the plurality of first test element group patterns included in each of the subset of chip regions of the shot group include a plurality of test patterns configured to provide a plurality of different tests of the semiconductor device (see FIG. 4 with respect to FIG. 8-9).
Regarding claim 4, Kim shows a semiconductor device, comprising, wherein a first subset of chip regions of the plurality of chip regions are included in a shot group, the shot group having an area covered by a single exposure in a photolithography process; the plurality of first align key patterns are included in the subset of chip regions of the shot group; and the plurality of first test element group patterns included in a second subset of chip regions of the plurality of chip regions of the shot group, the second subset of chip regions being different than the first subset of chip regions (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 5, Kim shows a semiconductor device, comprising: a first region including the plurality of first align key patterns and the plurality of first test element group patterns, the first region being included at arbitrary positions within each of the chip regions (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 6, Kim shows a semiconductor device, comprising, wherein the first region is at the same position within each of the chip regions (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 7, Kim shows a semiconductor device, comprising, wherein the first region has a rectangular ring shape surrounding at least one edge of each of the chip regions (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 8, Kim shows a semiconductor device, comprising, wherein the first region is at a corner of an inner edge within each of the chip regions (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 9, Kim shows a semiconductor device, comprising, wherein the semiconductor device include a plurality of unit devices, and the plurality of unit devices are included in a main region in each of the chip regions, the main region being different than the first region in each of the chip regions (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 10, Kim semiconductor device, comprising: a plurality of unit devices; a shot group of a substrate, the shot group including a plurality of chip regions, the shot group having an area covered by a single shot of a photolithography process; at least one scribe lane on the substrate, the at least one scribe lane surrounding the plurality of chip regions; a first region included in each of the chip regions, the first region including at least one of a plurality of first align key patterns and a plurality of first test element group patterns; and a main region included in each of the chip regions, the main region including the unit device the plurality of first align key patterns included in the chip regions of the shot group include a plurality of align key patterns used in different exposure processes, and the plurality of test element group patterns included in the chip regions of the shot group include a plurality of patterns configured to provide a plurality of different tests of the plurality of unit devices (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 11, Kim semiconductor device, comprising, wherein the at least one scribe lane includes at least one of a plurality of second align key patterns and a plurality of second test element group patterns (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 12, Kim semiconductor device, comprising wherein the at least one scribe lane does not include a plurality of second align key patterns and a plurality of second test element group patterns (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 13, Kim semiconductor device, comprising wherein each of the chip regions include the plurality of first align key patterns and the plurality of first test element group patterns (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 14, Kim semiconductor device, comprising, wherein the shot group includes a first subset of chip regions and a second subset of chip regions; the first subset of chip regions includes the plurality of first align key patterns; and the second subset of chip regions includes the plurality of first test element group patterns (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 15, Kim semiconductor device, comprising wherein the first region is at arbitrary positions within each of the chip regions (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 16, Kim semiconductor device, comprising wherein the first region is at the same position within each of the chip regions (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 17, Kim semiconductor device, comprising a plurality of unit devices; a chip region; at least one scribe lane surrounding the chip region; a first region included in the chip region, the first region including a plurality of first align key patterns and a plurality of first test element group patterns; and a main region included in the chip region, the main region including the plurality of unit devices (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 18, Kim semiconductor device, comprising wherein the at [east one scribe lane includes at least one of cut portions of a plurality of second align key patterns and cut portions of a plurality of cutting second test element group patterns (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 19, Kim semiconductor device, comprising wherein the at least one scribe lane does not include a plurality of second align key patterns and a plurality of second test element group patterns (see FIG. 4 with respect to FIG. 8-9 and related text).
Regarding claim 20, Kim semiconductor device, comprising wherein the first region is at an arbitrary position within the chip region (see FIG. 4 with respect to FIG. 8-9 and related text).
Response to Arguments
Applicant's arguments filed October 13, 2025 have been fully considered but they are not persuasive. Applicants assert that in remark page 9, a plurality of first align key patterns and a plurality of first test element group patterns not included in the plurality of chip regions however Kim only disclosed alignment marks in the scribe line region. The limitations of “include and region” often have multiple meanings. The Examiner has given the claim the broadest, reasonable interpretation, per MPEP 2111, and the align key patterns considered include even though physical location of the align key may not directly on the chip region.
It is for at least the reason above, the claims stand rejected as set forth in prior office action.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893