02DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to Applicant’s Amendment/Request for Reconsideration after Non-final Rejection filed on 6/16/2026 and IDS filed on 6/16/2026 and 5/26/2026. Claims 1-19,21 are pending, wherein claim 20 has been cancelled and claim 21 has been newly added.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-6, 9, 11,13-14, 17, 21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kukal et al. (US Patent No. 10,558,780 B1).
As per claims 1,3, 9,11,17 Fig. 1B illustrates the elements of the claims:
receiving a circuit specification specifying one or more components comprising one or more corresponding identifiers (circuits shown in top row with their various labels or identifiers, i.e., 124A, 102A, 112A) are received by the computing system 100A;
generating one or more schematic symbols (with symbol names or labels) for the one or more components, wherein the one or more schematic symbols are associated with the one or more corresponding identifiers (i.e., bottom circuit symbols names or labels 126A, 130A, 128A—see col. 10, lines 19-62, which includes identifiers and electrical properties or attributes) which are then read by the computing system and placed in the schematic design (i.e., in schematic representation); wherein the computer system comprising one or more processors, non-transitory computer-readable storage medium are further discussed in col. 23, lines 6-38).
As per claims 5-6,13-14, Kukal et al. disclose all of the elements of claims 1, 9 and 17, from which the respective claims depend, as discussed in the rejection of claims 1, 9 and 17 above; wherein the one or more components includes resistors, capacitors (see Figs. 3A-3B) which include the attributes or properties values (i.e., resistances or capacitances being attributes or properties of the capacitors and resistors as is known in the art which are further described in col. 11, lines 29-36).
As per claim 21, the circuit specification is a netlist is further described in col. 1, lines 38-50, and col. 3, line 26 to co. 5, line 50, wherein the extracted views and schematic still contain circuit components and their connections/interconnections, which are considered as a form of netlist.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2,4,1-8,12,15-16,18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kukal et al. (US Patent No. 10,558,780 B1) in view of Kugel et al. (US Patent Application Publication No. 2014/0130004 A1).
As per claims 2,4,10,12,18-19, Kukal et al. disclose all of the elements of claims 1, 9 and 17, from which the respective claims depend, as discussed in the rejection of claims 1, 9 and 17 above; wherein Kukal et al. further make of the identifiers/symbols to obtain the corresponding attributes or properties of the circuit (see col. 9, lines 15-38; col. 11, lines 29-37; col. 15, lines 1-11); but failed to particular teach that the identifiers/symbols encode one or more attribute values. The encoding or inclusion of the type of devices (i.e., transistors, resistors, capacitors) being part of the component’s identifier, along with their attributes values (i.e., number of fingers, gate width, resistance, capacitance) are known in the art as further taught by Kugel et al. for user’s or designer’s convenience (see paragraphs [0056]-[0058], [0074]-[0076]). It would have been obvious to one ordinary skilled in the art at the time of effective filing date of the invention to further incorporate the teachings of Kugel et al. of encoding or including the type of devices as well as their attribute values as part of the names or identifiers, into the method/system of Kukal et al. because such incorporation would allow convenience to the user or designer (i.e., to easily understand and/or verify the circuit design).
As per claims 7-8,15-16, Kukal et al. disclose all of the elements of claims 1, 9 and 17, from which the respective claims depend, as discussed in the rejection of claims 1, 9 and 17 above, but failed to particularly teach that the one or more components comprise a transistor and the one or more attributes being a gate width and number of fingers. Kugel et al. teach circuit design having various types of devices or components, such as transistors, resistors, capacitors, which have their identifiers or names as part of the component’s identifier, along with their attributes values (i.e., number of fingers, gate width, resistance, capacitance) (see paragraphs [0056]-[0058], [0074]-[0076]). It would have been obvious to one ordinary skilled in the art at the time of effective filing date of the invention to further incorporate identifies for transistors elements as known in the art of circuit design and includes these information as well as their attributes as part of the names or identifiers, as taught by Kugel et al., into the method/system of Kukal et al. because such incorporation would allow convenience to the user or designer (i.e., to easily understand and/or verify the circuit design).
Remarks
As per claims 1, 3, 5-6, 9, 11,13-14, 17, 20, Applicant argued that Kubal et al. failed to anticipate the independent claims 1,9,17 because Kubal et al. discloses a system to extract information from schematics and a layout for analysis, whereas the present claims pertains to a system for generating schematics from a circuit specification (e.g., a netlist to a schematic), wherein Kubal is directed to a completely different subject matter, namely predicting electrical behavior of an electronic design based on information extracted from a schematic and layout, failing to disclose the circuit components comprising identifiers, which are used to set attributes of the schematic. The Examiner is not persuaded. Although the Examiner agrees that Kubal et al. solve different problems, in so doing Kubal et al. still generate one or more schematic symbols which are associated with the one or more corresponding identifiers, reading the identifiers associated with the one or more schematic systems and inserting a schematic representation in which one or more attributes of the schematic representation for the one or more components are based on the identifiers associated with the schematic symbols as claimed (see rejections of claims 1, 9 and 17 above; col. 13, lines 46-60 for identifying a schematic circuit component design from the circuit specification, i.e., schematic design and the layout; col. 13, line 61 col. 14, line 5-- the generation or adaptation of the schematic-driven extracted view is achieved specifically by "placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information"; col. 14, lines 6-10-- This ensures the electronic design parameters can be altered or updated based directly upon the output of performing simulations or engineering design checks on that modified extracted view). That is, the circuit specification being received are the schematic design and the layout information, which are also considered circuit specification, which are also a form of netlist (i.e., circuit components and their interconnections/connections as applied to new claim 21). Accordingly, although the problem being solved may be different from Applicant’s claimed invention, the steps/operations for generating the electronic components schematic are disclosed by Kubal et al. as previously indicated.
As per claim(s) 2,4,1-8,12,15-16,18-19, Applicant argued that Kukal et al. (US Patent No. 10,558,780 B1) in view of Kugel et al. (US Patent Application Publication No. 2014/0130004 A1) failed to teach a circuit specification specifying components comprising identifiers, where the identifiers from the circuit specification are used to set attributes of the schematic as claimed, wherein Kugel et al. was relied on by the examiner for disclosing "identifiers/symbols encode one or more attribute values as to at least claim 2, which Applicant refutes. The Examiner is not persuaded. As discussed in section paragraph 8 above, Kugel et al. do teach Applicant’s claimed invention, wherein Kugel et al. provide for the missing elements for the reasons previously indicated.
As per claim 21, the claim is newly rejected as being necessitated by Applicant’s amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHALLAKA KIK whose telephone number is (571)272-1895. The examiner can normally be reached Maxiflex Mon-Fri 8:30AM-5PM.
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P. O. Box 1450
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/PHALLAKA KIK/Primary Examiner, Art Unit 2851 September 30, 2026
