DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application filed on 5/8/2023 and IDS filed on 5/8/2023, 10/26/2023, 3/25/2024. 6/21/2024, 12/16/2024, 6/6/2025, 7/25/2025, 12/02/2025, and 2/16/2026. Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-6, 9, 11,13-14, 17, 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kukal et al. (US Patent No. 10,558,780 B1).
As per claims 1,3, 9,11,17 Fig. 1B illustrates the elements of the claims:
receiving a circuit specification specifying one or more components comprising one or more corresponding identifiers (circuits shown in top row with their various labels or identifiers, i.e., 124A, 102A, 112A) are received by the computing system 100A;
generating one or more schematic symbols (with symbol names or labels) for the one or more components, wherein the one or more schematic symbols are associated with the one or more corresponding identifiers (i.e., bottom circuit symbols names or labels 126A, 130A, 128A—see col. 10, lines 19-62, which includes identifiers and electrical properties or attributes) which are then read by the computing system and placed in the schematic design (i.e., in schematic representation); wherein the computer system comprising one or more processors, non-transitory computer-readable storage medium are further discussed in col. 23, lines 6-38).
As per claims 5-6,13-14,20, Kukal et al. disclose all of the elements of claims 1, 9 and 17, from which the respective claims depend, as discussed in the rejection of claims 1, 9 and 17 above; wherein the one or more components includes resistors, capacitors (see Figs. 3A-3B) which include the attributes or properties values (i.e., resistances or capacitances being attributes or properties of the capacitors and resistors as is known in the art which are further described in col. 11, lines 29-36).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2,4,1-8,12,15-16,18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kukal et al. (US Patent No. 10,558,780 B1) in view of Kugel et al. (US Patent Application Publication No. 2014/0130004 A1).
As per claims 2,4,10,12,18-19, Kukal et al. disclose all of the elements of claims 1, 9 and 17, from which the respective claims depend, as discussed in the rejection of claims 1, 9 and 17 above; wherein Kukal et al. further make of the identifiers/symbols to obtain the corresponding attributes or properties of the circuit (see col. 9, lines 15-38; col. 11, lines 29-37; col. 15, lines 1-11); but failed to particular teach that the identifiers/symbols encode one or more attribute values. The encoding or inclusion of the type of devices (i.e., transistors, resistors, capacitors) being part of the component’s identifier, along with their attributes values (i.e., number of fingers, gate width, resistance, capacitance) are known in the art as further taught by Kugel et al. for user’s or designer’s convenience (see paragraphs [0056]-[0058], [0074]-[0076]). It would have been obvious to one ordinary skilled in the art at the time of effective filing date of the invention to further incorporate the teachings of Kugel et al. of encoding or including the type of devices as well as their attribute values as part of the names or identifiers, into the method/system of Kukal et al. because such incorporation would allow convenience to the user or designer (i.e., to easily understand and/or verify the circuit design).
As per claims 7-8,15-16, Kukal et al. disclose all of the elements of claims 1, 9 and 17, from which the respective claims depend, as discussed in the rejection of claims 1, 9 and 17 above, but failed to particularly teach that the one or more components comprise a transistor and the one or more attributes being a gate width and number of fingers. Kugel et al. teach circuit design having various types of devices or components, such as transistors, resistors, capacitors, which have their identifiers or names as part of the component’s identifier, along with their attributes values (i.e., number of fingers, gate width, resistance, capacitance) (see paragraphs [0056]-[0058], [0074]-[0076]). It would have been obvious to one ordinary skilled in the art at the time of effective filing date of the invention to further incorporate identifies for transistors elements as known in the art of circuit design and includes these information as well as their attributes as part of the names or identifiers, as taught by Kugel et al., into the method/system of Kukal et al. because such incorporation would allow convenience to the user or designer (i.e., to easily understand and/or verify the circuit design)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHALLAKA KIK whose telephone number is (571)272-1895. The examiner can normally be reached Maxiflex Mon-Fri 8:30AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 5712727483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Any response to this action should be mailed to:
Commissioner for Patents
P. O. Box 1450
Alexandria, VA 22313-1450
or faxed to:
571-273-8300
/PHALLAKA KIK/Primary Examiner, Art Unit 2851 March 30, 2026
Prosecution Insights