CTFR 18/314,245 CTFR 88782 DETAILED ACTION Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 1-9, 13-15, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Huang et al. (US 20210407999; herein “Huang”) in view of Chen et al. (US 20240363553; herein “Chen”) . Regarding claim 1, Huang teaches in Figs. 2 and 3 and related text a three-dimensional (3D) dual circuit structure, comprising: a first forksheet structure comprising a first semiconductor slab (e.g. 203 of upper forksheet structure, see [0037]; see also 306B/306A and [0055]); a second forksheet structure comprising a second semiconductor slab (e.g. 203 of lower forksheet structure; see also 306A/306B), and disposed on a first side of, in a first direction (e.g. vertical), the first forksheet structure; and a dividing wall (201, see [0037]) bisecting each of the first semiconductor slab and the second semiconductor slab, wherein the dividing wall extends in the first direction and in a second direction (e.g. horizontal as shown in Fig. 2(i), i.e. direction of source to drain nanosheet extension) orthogonal to the first direction, wherein: the first semiconductor slab bisected by the dividing wall comprises a first slab portion (e.g. upper left side portion, as oriented in Fig. 2(ii)) comprising a first semiconductor type on a first side of the dividing wall and a second slab portion (e.g. upper right side, as oriented in Fig. 2(ii)) comprising a second semiconductor type on a second side of the dividing wall; the second semiconductor slab bisected by the dividing wall comprises a third slab portion (e.g. lower left side portion, as oriented in Fig. 2(ii)) comprising a third semiconductor type on the first side of the dividing wall and a fourth slab portion (e.g. lower right side portion, as oriented in Fig. 2(ii)) comprising a fourth semiconductor type on the second side of the dividing wall (see [0046]); and a first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is the same semiconductor type as the first semiconductor type (see [0063]); the first slab portion extends in the second direction of the dividing wall (horizontal as oriented in Fig. 2(i)) from a first gate to a second gate (from first 204 at left of Fig. 2(i) to second 204 at right of Fig. 2(i)); and the second slab portion extends in the second direction of the dividing wall from a first gate to a second gate (from first 204 at left of Fig. 2(i) to second 204 at right of Fig. 2(i)). Huang does not disclose the first slab portion extends in the second direction from a first dummy gate to a second dummy gate; the second slab portion extends in the second direction of the dividing wall from the first dummy gate to the second dummy gate. In the same field of endeavor, Chen teaches in Fig. 6A and related text a semiconductor device comprising a slab portion (portion comprising nanosheets, see [0031]) that extends in the second direction (i.e. direction of source to drain nanosheet extension) of the dividing wall from a first dummy gate (240 on right) to a second dummy gate (240 on left) (note that the end 240 are interpreted as dummy gates because they will not control a source to drain channel current, as evidenced by the lack of a source/drain region on the far side of each dummy gate). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang by having the in order to provide a structure which wraps around and supports the end portions of the nanosheets at the peripheral ends of the device which employs manufacturing steps already being performed. The limitations “the first (second) slab portion extends in the second direction of the dividing wall from the first dummy gate to the second dummy gate” is taught by the combination of the nanosheets having dummy gates at the ends, as shown by Chen, and the device having nanosheets in a first slab and a second slab which are vertically stacked and share gates, as shown by Huang. Regarding claim 2, Huang further discloses a second one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is the same semiconductor type as a third one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0063]). Regarding claim 3, Huang further discloses wherein the second semiconductor type is the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0063]). Regarding claim 4, Huang further discloses wherein the third semiconductor type is the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0063]). Regarding claim 5, Huang further discloses wherein the fourth semiconductor type is the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0063]). Regarding claim 6, Huang further discloses the first forksheet structure further comprising: a first gate (e.g. 204 of upper left, see [0037]); and a second gate (e.g. 204 of upper right); wherein: the first gate is disposed around the first semiconductor slab in the first slab portion; the second gate is disposed around the first semiconductor slab in the second slab portion; and the first gate is separated from the second gate by the dividing wall (201). Regarding claim 7, Huang further discloses the second forksheet structure further comprising: a third gate (e.g. 208 of lower left, see [0037]); and a fourth gate (e.g. 208 of lower right); wherein: the third gate is disposed around the second semiconductor slab in the third slab portion; the fourth gate is disposed around the second semiconductor slab in the fourth slab portion; and the third gate is separated from the fourth gate by the dividing wall (201). Regarding claim 8, Huang further discloses a first type work function metal (e.g. P-WFM, see [0051]) disposed between the first gate and the first semiconductor slab in the first slab portion; and the first type work function metal disposed in a first one of the second slab portion, the third slab portion, and the fourth slab portion comprising the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0051]). Regarding claim 9, Huang further discloses a second type work function metal (e.g. N-WFM, see [0051]), different from the first type work function metal, disposed in a second one and a third one of the second slab portion, the third slab portion, and the fourth slab portion (see [0051]). Regarding claims 13-15, Huang further comprises a first contact layer (206, 216, and metallization therein, see [0038]-[0040]) disposed on the first forksheet structure, the first contact layer comprising: a first gate contact (220 left, see [0039]) coupled to the first gate (204 of upper left); and a second gate contact (220 right) coupled to the second gate (204 or upper right); and a second contact layer (230, 210, and metallization therein, see [0038]-[0040]) disposed on the second forksheet structure, the second contact layer comprising: a third gate contact (214 to 208 left, see [0039]; note that more than one 214, respectively coupled to more than one gate, is disclosed as possible embodiments) coupled to the third gate; and a fourth gate contact (214, see [0039]) coupled to the fourth gate; a first source/drain (a first 226, see [0038]) coupled to of the first semiconductor slab in the first slab portion on a first side of the first gate; a second source/drain (a second 226) coupled to each of the first semiconductor slab in the first slab portion on a second side of the first gate; a third source/drain (a third 226) coupled to of the first semiconductor slab in the second slab portion on a first side of the second gate; a fourth source/drain (a fourth 226) coupled to of the first semiconductor slab in the second slab portion on a second side of the second gate; a fifth source/drain (a first 224, see [0038]) coupled to of the second semiconductor slab in the third slab portion on a first side of the third gate; a sixth source/drain (a second 224) coupled to of the second semiconductor slab in the third slab portion on a second side of the third gate; a seventh source/drain (a third 224) coupled to of the second semiconductor slab in the fourth slab portion on a first side of the fourth gate; and an eighth source/drain (a fourth 224) coupled to of the second semiconductor slab in the fourth slab portion on a second side of the fourth gate; the first contact layer further comprising: a first source/drain contact (first 206/238/236, see [0038] and [0040]; note that one or more 206/238/236, respectively coupled to one or more 226, is disclosed as possible embodiments) coupled to the first source/drain; a second source/drain contact (second 206/238/236) coupled to the second source/drain; a third source/drain contact (third 206/238/236) coupled to the third source/drain; and a fourth source/drain contact (fourth 206/238/236) coupled to the fourth source/drain; and the second contact layer further comprising: a fifth source/drain contact (first 230/234/232, see [0038] and [0040]; ; note that one or more 230/234/232, respectively coupled to one or more 224, is disclosed as possible embodiments and one or more 234/232, respectively coupled to one or more 230, is disclosed as possible embodiments) coupled to the fifth source/drain; a sixth source/drain contact (second 230/234/232) coupled to the sixth source/drain; a seventh source/drain contact (third 230/234/232) coupled to the seventh source/drain; and an eighth source/drain contact (fourth 230/234/232) coupled to the eighth source/drain. In the alternative, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang to have the gate contact and the source/drain contacts in addition to the ones explicitly shown in Fig. 2(ii)-(iii), because it is an obvious matter of design choice to achieve a circuit design which is desirable according to circumstances. Regarding claim 18, Huang further disclose the 3D dual circuit structure of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter (see [0087]). Regarding claim 20, Huang discloses the claimed invention in substantially the same manner and for substantially the same reasons as applied to claim 1 above . 07-22-aia AIA Claim (s) 10, 12 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chen , as applied to claim 7 above, and further in view of Lilak et al. (US 20210296315; herein “Lilak”) . Regarding claims 10, 12 and 17, Huang further discloses the first forksheet structure is disposed in a first dielectric layer (layer/portion of 202 in which upper forksheet is disposed, see [0037]); the second forksheet structure is disposed in a second dielectric layer (layer/portion of 202 in which lower forksheet is disposed; but does not explicitly disclose a bonding layer, wherein: the bonding layer is disposed between the first dielectric layer and the second dielectric layer; wherein the dividing wall extends through the bonding layer; the first gate is electrically isolated from the third gate by the bonding layer; and the second gate is electrically isolated from the fourth gate by the bonding layer. In the same field of endeavor, Lilak teaches in Fig. 2B and related text a 3D circuit structure comprising a bonding layer (214, see [0043]), wherein: the bonding layer is disposed between the first dielectric layer (layer/portion of 203 in which upper forksheet structure is disposed) and the second dielectric layer (layer/portion of 203 in which lower forksheet structure is disposed); wherein the dividing wall (210, see [0045]) extends through the bonding layer. the first gate (gate of 220C) is electrically isolated from the third gate (gate of 220A) by the bonding layer; and the second gate (gate of 220 D) is electrically isolated from the fourth gate (gate of 220B) by the bonding layer (see Fig. 2B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang by having a bonding layer disposed between the first dielectric layer and the second dielectric layer, the dividing wall extending through the bonding layer, the first gate is electrically isolated from the third gate by the bonding layer, and the second gate is electrically isolated from the fourth gate by the bonding layer, as taught by Lilak, in order to eliminate or minimize an alignment error by providing a single dividing wall (see Lilak [0051]-[0052]) and to allow for desired circuit design as it relates to interconnection between various element. Note that the limitation “bonding ” claims recites a process, however the claim is directed to a product. Therefore, this limitation is considered to be product by process limitations. "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe , 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113. Additionally, the limitation "bonding,” is a functional feature of the layer. While features of an apparatus may be recited either structurally or functionally, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. See MPEP 2114.I and 2112.01 . 07-22-aia AIA Claim (s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chen , as applied to claim 15 above, and further in view of Liu et al. (US 20230413505; herein “Liu”) . Regarding claim 16, Huang further discloses a first via (244, see [0041]) coupling the first source/drain contact (238) to backside contacts; but does not explicitly disclose the first via coupling the first source/drain contact to the fifth source/drain contact; and a second via coupling the third source/drain contact to the seventh source/drain contact. In the same field of endeavor, Liu teaches in Fig. 2 and related text a 3D dual circuit structure comprising coupling the first source/drain contact to the fifth source/drain contact (see Fig. 2); and coupling the third source/drain contact to the seventh source/drain contact (see Fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang by a coupling the first source/drain contact to the fifth source/drain contact and coupling the third source/drain contact to the seventh source/drain contact in order to achieve a circuit structure for a 3D SRAM circuit. The limitation “a first via coupling the first source/drain contact to the fifth source/drain contact” is therefore taught by the combination of the first source the first source/drain contact to the fifth source/drain contact, as shown by Liu, and the first via coupling the first source/drain contact to backside contacts and the fifth source/drain contacts being backside contacts, as shown by Huang. Additionally, as outlined above in the rejection of claims 13-15, Huang teaches the seventh source/drain contact being a backside contact in the second contact layer. This in combination with the teaching of a via being used to couple a frontside source/drain contact with backside contacts taught by Huang, and the coupling of the third source/drain contact to the seventh source/drain contact taught by Liu, would make it obvious to one of ordinary skill in the art to arrive at a second via coupling the third source/drain contact to the seventh source/drain contact in order to achieve a circuit structure for a 3D SRAM circuit employing a connection of frontside and backside contacts taught by Huang. It is noted that modification of the device to achieve a circuit design which is desirable according to circumstances is an obvious matter of design choice. Response to Arguments Applicant's arguments filed 4/13/2026 have been fully considered but are moot in view of the new grounds of rejection presented above. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896 Application/Control Number: 18/314,245 Page 2 Art Unit: 2896 Application/Control Number: 18/314,245 Page 3 Art Unit: 2896 Application/Control Number: 18/314,245 Page 4 Art Unit: 2896 Application/Control Number: 18/314,245 Page 5 Art Unit: 2896 Application/Control Number: 18/314,245 Page 6 Art Unit: 2896 Application/Control Number: 18/314,245 Page 7 Art Unit: 2896 Application/Control Number: 18/314,245 Page 8 Art Unit: 2896 Application/Control Number: 18/314,245 Page 9 Art Unit: 2896 Application/Control Number: 18/314,245 Page 10 Art Unit: 2896 Application/Control Number: 18/314,245 Page 11 Art Unit: 2896 Application/Control Number: 18/314,245 Page 12 Art Unit: 2896 Application/Control Number: 18/314,245 Page 13 Art Unit: 2896
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