DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species A in the reply filed on 11/25/2025 is acknowledged. The traversal is on the ground(s) that the process cannot be used to make another materially different product and the product cannot be made by another materially different process and asserts a table mapping limitations of claims 1 and 19, and that the examiner has not explained the serious search burden as required by MPEP 808.02 and 808.02(A).
This is not found persuasive because, although there are similar limitations between claims 1 and 19, the method of claim 19 recites “forming a dividing wall bisecting the at least one first semiconductor slab and the at least one second semiconductor slab in a second direction” which requires the first and second semiconductor slabs to be present and then bisected by the dividing wall. This is in contrast to the device claim which implies nor requires any such order. Accordingly, the product as claimed can be made by another and materially different process such as forming a dividing wall, forming two first semiconductor slabs on either side of the dividing wall, and forming two second semiconductor slabs on either side of the dividing wall instead of forming a dividing wall bisecting a first semiconductor slab and a second semiconductor slab. Additionally, the examiner has explained the serious search burden due to the inventions having acquired a separate status in the art in view of their different classification and the inventions requiring a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search queries) (see the Requirement for Restriction mailed 10/2/2025, pages 2 and 3). The requirement is still deemed proper and is therefore made FINAL.
Applicant is reminded that when all product claims are found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims will be rejoined, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104.
Claims 11 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 11/25/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s)1-10, 12-18 and 20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “a dividing wall bisecting each of the at least one first semiconductor slab and the at least one second semiconductor slab in a second direction orthogonal to the first direction,” is unclear as to if it requires dividing each of the first semiconductor slabs (plural) and each of the second semiconductor slabs (plural). Further, it is unclear as to the required direction. Specifically, it is unclear as to if it is intended to claim the bisecting in the second direction (i.e. the direction of the cutting in the method, understood to be the Z direction of Figs. 1A-C), if it is intended to be the dividing in the second direction (i.e. a longitudinal direction of the dividing wall, understood as the X direction of Figs. 1A-C), or if it is intended as the first and second slab portions being in the second direction (i.e. the first semiconductor slab is divided such that first and second slab portions are in the X direction).
Regarding claim 1, the limitations “the first (second) semiconductor slab,” are unclear as to how it is related to the previously recited “at least one (second)semiconductor slab.”
Regarding claim 14, the limitations “each of the at least one first semiconductor slab in the first (second) slab portion,” are unclear as to which semiconductor slab(s) are required. Specifically, “each” appears to require plural, however “slab” is recited as singular. Additionally, claim 1 requires “the first semiconductor slab” to comprise a first slab portion and a second slab portion, but does not require each first slab of the at least one first semiconductor slabs to be in the first slab portion and the second slab portion. The limitation of this claim, however, appears to require each first slab of the at least one first semiconductor slabs to be in the first slab portion and each first slab of the at least one first semiconductor slabs to be in the second slab portion. It is therefore unclear what is required.
Regarding claim 14, the limitations “each of the at least one second semiconductor slab in the third (fourth) slab portion,” are unclear as to which semiconductor slab(s) are required. Specifically, “each” appears to require plural, however “slab” is recited as singular. Additionally, claim 1 requires “the second semiconductor slab” to comprise a third slab portion and a fourth slab portion, but does not require each second slab of the at least one second semiconductor slabs to be in the third slab portion and the fourth slab portion. The limitation of this claim, however, appears to require each second slab of the at least one second semiconductor slabs to be in the third slab portion and each second slab of the at least one second semiconductor slabs to be in the fourth slab portion. It is therefore unclear what is required.
Regarding claim 17, the limitations “the first (second) gate is electrically isolated from the third (fourth) gate by the bonding layer,” are unclear as to what is required by “electrically isolated from.” Specifically, while the bonding layer 124 appears to physically separate the gates, the first and third (second and fourth) gates appear to be coupled in Fig. 1C by an unlabeled element in 124, and are explicitly coupled in all the other disclosed embodiments. Furthermore, the pairs of gates are disclosed as being CMOS circuits, which conventionally have coupled gates. Therefore, it would not appear that the gates are electrically isolated, and it is unclear as to the proper interpretation of the claimed limitation.
Regarding claim 20, the limitation “a dividing wall bisecting the at least one first semiconductor slab in a second direction orthogonal to the first direction…and bisecting the at least one second semiconductor slab in the second direction,” is unclear as to the required direction. Specifically, it is unclear as to if it is intended to claim the bisecting in the second direction (i.e. the direction of the cutting in the method, understood to be the Z direction of Figs. 1A-C), if it is intended to be the dividing in the second direction (i.e. a longitudinal direction of the dividing wall, understood as the X direction of Figs. 1A-C), or if it is intended as the first and second slab portions being in the second direction (i.e. the first semiconductor slab is divided such that first and second slab portions are in the X direction).
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20210407999; herein “Huang”)
Regarding claim 1, Huang teaches in Figs. 2 and 3 and related text a three-dimensional (3D) dual circuit structure, comprising:
a first forksheet structure comprising at least one first semiconductor slab (e.g. 203 of upper forksheet structure, see [0037]; see also 306B/306A and [0055]);
a second forksheet structure comprising at least one second semiconductor slab (e.g. 203 of lower forksheet structure; see also 306A/306B), and disposed on a first side of, in a first direction (e.g. vertical), the first forksheet structure; and
a dividing wall (201, see [0037]) bisecting each of the at least one first semiconductor slab and the at least one second semiconductor slab in a second direction orthogonal to the first direction (e.g. horizontal),
wherein:
the first semiconductor slab bisected by the dividing wall comprises a first slab portion (e.g. upper left side portion, as oriented in Fig. 2(ii)) comprising a first semiconductor type on a first side of the dividing wall and a second slab portion (e.g. upper right side, as oriented in Fig. 2(ii)) comprising a second semiconductor type on a second side of the dividing wall;
the second semiconductor slab bisected by the dividing wall comprises a third slab portion (e.g. lower left side portion, as oriented in Fig. 2(ii)) comprising a third semiconductor type on the first side of the dividing wall and a fourth slab portion (e.g. lower right side portion, as oriented in Fig. 2(ii)) comprising a fourth semiconductor type on the second side of the dividing wall (see [0046]); and
a first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is the same semiconductor type as the first semiconductor type (see [0063]).
Regarding claim 2, Huang further discloses a second one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is the same semiconductor type as a third one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0063]).
Regarding claim 3, Huang further discloses wherein the second semiconductor type is the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0063]).
Regarding claim 4, Huang further discloses wherein the third semiconductor type is the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0063]).
Regarding claim 5, Huang further discloses wherein the fourth semiconductor type is the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0063]).
Regarding claim 6, Huang further discloses the first forksheet structure further comprising:
a first gate (e.g. 204 of upper left, see [0037]); and
a second gate (e.g. 204 of upper right);
wherein:
the first gate is disposed around the at least one first semiconductor slab in the first slab portion;
the second gate is disposed around the at least one first semiconductor slab in the second slab portion; and
the first gate is separated from the second gate by the dividing wall (201).
Regarding claim 7, Huang further discloses the second forksheet structure further comprising:
a third gate (e.g. 208 of lower left, see [0037]); and
a fourth gate (e.g. 208 of lower right);
wherein:
the third gate is disposed around the at least one second semiconductor slab in the third slab portion;
the fourth gate is disposed around the at least one second semiconductor slab in the fourth slab portion; and
the third gate is separated from the fourth gate by the dividing wall (201).
Regarding claim 8, Huang further discloses
a first type work function metal (e.g. P-WFM, see [0051]) disposed between the first gate and the at least one first semiconductor slab in the first slab portion; and
the first type work function metal disposed in a first one of the second slab portion, the third slab portion, and the fourth slab portion comprising the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type (see [0051]).
Regarding claim 9, Huang further discloses a second type work function metal (e.g. N-WFM, see [0051]), different from the first type work function metal, disposed in a second one and a third one of the second slab portion, the third slab portion, and the fourth slab portion (see [0051]).
Regarding claim 18, Huang further disclose the 3D dual circuit structure of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter (see [0087]).
Regarding claim 20, Huang discloses the claimed invention in substantially the same manner and for substantially the same reasons as applied to claim 1 above.
Claim Rejections - 35 USC § 102/35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Huang.
Regarding claims 13-15, Huang further comprises
a first contact layer (206, 216, and metallization therein, see [0038]-[0040]) disposed on the first forksheet structure, the first contact layer comprising:
a first gate contact (220 left, see [0039]) coupled to the first gate (204 of upper left); and
a second gate contact (220 right) coupled to the second gate (204 or upper right); and
a second contact layer (230, 210, and metallization therein, see [0038]-[0040]) disposed on the second forksheet structure, the second contact layer comprising:
a third gate contact (214 to 208 left, see [0039]; note that more than one 214, respectively coupled to more than one gate, is disclosed as possible embodiments) coupled to the third gate; and
a fourth gate contact (214, see [0039]) coupled to the fourth gate;
a first source/drain (a first 226, see [0038]) coupled to each of the at least one first semiconductor slab in the first slab portion on a first side of the first gate;
a second source/drain (a second 226) coupled to each of the at least one first semiconductor slab in the first slab portion on a second side of the first gate;
a third source/drain (a third 226) coupled to each of the at least one first semiconductor slab in the second slab portion on a first side of the second gate;
a fourth source/drain (a fourth 226) coupled to each of the at least one first semiconductor slab in the second slab portion on a second side of the second gate;
a fifth source/drain (a first 224, see [0038]) coupled to each of the at least one second semiconductor slab in the third slab portion on a first side of the third gate;
a sixth source/drain (a second 224) coupled to each of the at least one second semiconductor slab in the third slab portion on a second side of the third gate;
a seventh source/drain (a third 224) coupled to each of the at least one second semiconductor slab in the fourth slab portion on a first side of the fourth gate; and
an eighth source/drain (a fourth 224) coupled to each of the at least one second semiconductor slab in the fourth slab portion on a second side of the fourth gate;
the first contact layer further comprising:
a first source/drain contact (first 206/238/236, see [0038] and [0040]; note that one or more 206/238/236, respectively coupled to one or more 226, is disclosed as possible embodiments) coupled to the first source/drain;
a second source/drain contact (second 206/238/236) coupled to the second source/drain;
a third source/drain contact (third 206/238/236) coupled to the third source/drain; and
a fourth source/drain contact (fourth 206/238/236) coupled to the fourth source/drain; and
the second contact layer further comprising:
a fifth source/drain contact (first 230/234/232, see [0038] and [0040]; ; note that one or more 230/234/232, respectively coupled to one or more 224, is disclosed as possible embodiments and one or more 234/232, respectively coupled to one or more 230, is disclosed as possible embodiments) coupled to the fifth source/drain;
a sixth source/drain contact (second 230/234/232) coupled to the sixth source/drain;
a seventh source/drain contact (third 230/234/232) coupled to the seventh source/drain; and
an eighth source/drain contact (fourth 230/234/232) coupled to the eighth source/drain.
In the alternative, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang to have the gate contact and the source/drain contacts in addition to the ones explicitly shown in Fig. 2(ii)-(iii), because it is an obvious matter of design choice to achieve a circuit design which is desirable according to circumstances.
Claim Rejections - 35 USC § 103
Claim(s) 10, 12 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 7 above, and in view of Lilak et al. (US 20210296315; herein “Lilak”).
Regarding claims 10, 12 and 17, Huang further discloses
the first forksheet structure is disposed in a first dielectric layer (layer/portion of 202 in which upper forksheet is disposed, see [0037]);
the second forksheet structure is disposed in a second dielectric layer (layer/portion of 202 in which lower forksheet is disposed;
but does not explicitly disclose
a bonding layer, wherein:
the bonding layer is disposed between the first dielectric layer and the second dielectric layer;
wherein the dividing wall extends through the bonding layer;
the first gate is electrically isolated from the third gate by the bonding layer; and
the second gate is electrically isolated from the fourth gate by the bonding layer.
In the same field of endeavor, Lilak teaches in Fig. 2B and related text a 3D circuit structure comprising
a bonding layer (214, see [0043]), wherein:
the bonding layer is disposed between the first dielectric layer (layer/portion of 203 in which upper forksheet structure is disposed) and the second dielectric layer (layer/portion of 203 in which lower forksheet structure is disposed);
wherein the dividing wall (210, see [0045]) extends through the bonding layer.
the first gate (gate of 220C) is electrically isolated from the third gate (gate of 220A) by the bonding layer; and
the second gate (gate of 220 D) is electrically isolated from the fourth gate (gate of 220B) by the bonding layer (see Fig. 2B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang by having a bonding layer disposed between the first dielectric layer and the second dielectric layer, the dividing wall extending through the bonding layer, the first gate is electrically isolated from the third gate by the bonding layer, and the second gate is electrically isolated from the fourth gate by the bonding layer, as taught by Lilak, in order to eliminate or minimize an alignment error by providing a single dividing wall (see Lilak [0051]-[0052]) and to allow for desired circuit design as it relates to interconnection between various element.
Note that the limitation “bonding ” claims recites a process, however the claim is directed to a product. Therefore, this limitation is considered to be product by process limitations. "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113. Additionally, the limitation "bonding,” is a functional feature of the layer. While features of an apparatus may be recited either structurally or functionally, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. See MPEP 2114.I and 2112.01.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 15 above, and in view of Liu et al. (US 20230413505; herein “Liu”).
Regarding claim 16, Huang further discloses
a first via (244, see [0041]) coupling the first source/drain contact (238) to backside contacts;
but does not explicitly disclose
the first via coupling the first source/drain contact to the fifth source/drain contact; and
a second via coupling the third source/drain contact to the seventh source/drain contact.
In the same field of endeavor, Liu teaches in Fig. 2 and related text a 3D dual circuit structure comprising
coupling the first source/drain contact to the fifth source/drain contact (see Fig. 2); and
coupling the third source/drain contact to the seventh source/drain contact (see Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang by a coupling the first source/drain contact to the fifth source/drain contact and coupling the third source/drain contact to the seventh source/drain contact in order to achieve a circuit structure for a 3D SRAM circuit. The limitation “a first via coupling the first source/drain contact to the fifth source/drain contact” is therefore taught by the combination of the first source the first source/drain contact to the fifth source/drain contact, as shown by Liu, and the first via coupling the first source/drain contact to backside contacts and the fifth source/drain contacts being backside contacts, as shown by Huang. Additionally, as outlined above in the rejection of claims 13-15, Huang teaches the seventh source/drain contact being a backside contact in the second contact layer. This in combination with the teaching of a via being used to couple a frontside source/drain contact with backside contacts taught by Huang, and the coupling of the third source/drain contact to the seventh source/drain contact taught by Liu, would make it obvious to one of ordinary skill in the art to arrive at a second via coupling the third source/drain contact to the seventh source/drain contact in order to achieve a circuit structure for a 3D SRAM circuit employing a connection of frontside and backside contacts taught by Huang. It is noted that modification of the device to achieve a circuit design which is desirable according to circumstances is an obvious matter of design choice.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 1/9/2026