Prosecution Insights
Last updated: April 19, 2026
Application No. 18/314,248

CORELESS SUBSTRATES AND MANUFACUTRING METHODS THEREOF

Final Rejection §103§112
Filed
May 09, 2023
Examiner
SWANSON, WALTER H
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Avago Technologies International Sales Pte. Ltd.
OA Round
2 (Final)
75%
Grant Probability
Favorable
3-4
OA Rounds
2y 5m
To Grant
85%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
608 granted / 815 resolved
+6.6% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
32 currently pending
Career history
847
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
48.5%
+8.5% vs TC avg
§102
23.5%
-16.5% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 815 resolved cases

Office Action

§103 §112
DETAILED ACTION AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response To First Action On Merits The 8 JAN 2026 amendments to claims 1 and 11 have been entered. The 8 JAN 2026 cancellation of claim 5 has been entered. Claim Objections Typographical errors: Claim 11, line 10, replace “a second plurality of electrical contacts” with “the second plurality of electrical contacts” (see line 8 of claim 11). Appropriate correction is required. Claim Rejections – 35 USC § 112 The 8 JAN 2026 amendments to claim 11 overcome the rejection noted in the previous Office action. New Grounds of Rejection A new ground of rejection, prior art reference XU et al. (US 20200266149), appears below. Claim Rejections - 35 USC § 103 See previous Office action for a quotation of 35 U.S.C. 103. Claims 1-4 and 6-16 are rejected under 35 U.S.C. 103 as obvious over XU et al. (US 20200266149; below, “XU”) with evidence from and/or in view of CHO et al. (US 20220108935; below, “CHO” – previously cited 19 NOV 2024 IDS noted prior art reference). At least “combining prior art elements”, “simple substitution”, “obvious to try”, and “applying a known technique to a known device” rationales support a conclusion of obviousness. MPEP § 2143(A)-(G). RE 1, XU, in FIGS. 1C, 3-5, and related text, e.g., Abstract, paragraphs [0001] to [0126], claims 1-20, discloses a semiconductor device (150) comprising: PNG media_image1.png 458 924 media_image1.png Greyscale a circuit (102) comprising a first plurality of electrical contacts (e.g., [0023]); and a substrate (196, e.g., [0033]) coupled to the circuit (102), the substrate (196) being characterized by a width of at least 50 mm (Regarding the underlined portion, the claim range of at least 50 mm is considered to be an obvious matter of finding an optimum workable range for some chosen design requirement utilizing the disclosure of Xu. Furthermore it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955). Finally, any difference in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co. Inc., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As evidence see Cho’s paragraph [0034].) and comprising a coreless substrate ([0033]), wherein the substrate (196) comprises: a coreless buildup material (ABF, e.g., [0036]); a top layer (136) comprising a second plurality of electrical contacts (118a-b) and a first organic material (e.g., [0035]), the second plurality of electrical contacts (118a-b) being coupled to the first plurality of electrical contacts (e.g., [0023]); a bottom layer (132) comprising a third plurality of electrical contacts (116, e.g., [0033]) and a second organic material (e.g., [0035]); and a plurality of substrate layers (134a-c) positioned between the top layer (136) and the bottom layer (132), the plurality of substrate layers (134a-c) comprising a fourth plurality of electrical contacts (126a-b, 128) configured to provide electrical connections (122/124) between the first plurality of electrical contacts (e.g., [0023]) and the third plurality of electrical contacts (116). RE 2, modified XU discloses the semiconductor device of claim 1, wherein the bottom layer (132) comprises a ball grid array (BGA) layer (e.g., [0033]). RE 3, modified XU discloses the semiconductor device of claim 1, wherein the bottom layer (132) comprises a land grid array (LGA) layer (e.g., [0033], [0104]). RE 4, modified XU discloses the semiconductor device of claim 1, wherein the substrate is free from an organic core material (e.g., [0033]). RE 6, modified XU discloses the semiconductor device of claim 1, wherein the top layer (136) comprises a solder mask material (e.g., [0035]). RE 7, modified XU discloses the semiconductor device of claim 1, wherein the plurality of substrate layers (134a-c) comprises a glass fiber material (e.g., Abstract, [0027]). RE 8, modified XU discloses the semiconductor device of claim 1, wherein the plurality of substrate layers (134a-c) comprises a hybrid material (e.g., [0036]). RE 9, modified XU discloses the semiconductor device of claim 1, wherein the plurality of substrate layers (134a-c) comprises a pre-preg composite material (e.g., [0036]). RE 10, modified XU discloses the semiconductor device of claim 1, wherein the substrate (196) consists of fewer than 20 layers (e.g., [0036]). RE 11, XU, in FIGS. 1C, 3-7O, and related text, e.g., Abstract, paragraphs [0001] to [0126], claims 1-20, discloses a semiconductor package (1000A) comprising: a first carrier layer (750, e.g., [0075]-[0077]); and a substrate (196) coupled to the first carrier layer (C1), the substrate (196) being characterized by a width of at least 70 mm (Regarding the underlined portion of claim 11, the claim range of at least 70 mm is considered to be an obvious matter of finding an optimum workable range … utilizing the disclosure of Xu. Moreover, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill …. In re Aller, 105 USPQ 233 (CCPA 1955). Finally, any difference in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co. Inc., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As evidence see Cho’s paragraph [0034].) and comprising a coreless substrate (196), wherein the substrate (196) comprises: a coreless buildup material (ABF, e.g., [0036]); a top layer (136) comprising a first plurality of electrical contacts (118a-b) and a first organic material (e.g., [0035]), a second plurality of electrical contacts (116, e.g., [0033]) being coupled (122/124) to the first plurality of electrical contacts (118a-b); a bottom layer (132) comprising a [sic, “the”] second plurality of electrical contacts (116, e.g., [0033]) and a second organic material (e.g., [0035]); and a plurality of substrate layers (134a-c, e.g., [0036]) positioned between the top layer (136) and the bottom layer (132), the plurality of substrate layers (134a-c) comprising a third plurality of electrical contacts (126a-b, 128). RE 12, modified XU discloses the semiconductor package of claim 11, wherein the substrate is free from an organic core material (e.g., [0033]). RE 13, modified XU discloses the semiconductor package of claim 11, wherein the top layer (136) comprises a solder mask material (e.g., [0035]). RE 14, modified XU discloses the semiconductor package of claim 11, wherein the bottom layer (132) comprises a ball grid array (BGA) layer (e.g., [003]). RE 15, modified XU discloses the semiconductor package of claim 11, wherein the first carrier layer (750) comprises a ceramic material, a glass material, or an organic material (e.g., [0075]). RE 16, modified XU discloses the semiconductor package of claim 11, wherein the first carrier layer (750) comprises a first surface and a second surface, the first surface being coupled to the bottom layer (132), the second surface being detached from a second carrier layer (Regarding the underlined portion of claim 16, applicants are reminded that the method of forming a device is not germane to the issue of patentability of the device itself. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985). Claims 1-4 and 6-16 are rejected. Response to Arguments Applicants’ 8 JAN 2023 rebuttal arguments (REM pages 6-7) are found to be unpersuasive in light of the arguments and positions detailed in the claim rejections supra. Additionally, the new ground of rejection was necessary due to the applicants’ amendments. Applicants’ arguments vis-à-vis patentability have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Walter Swanson whose telephone number is (571) 270-3322. The examiner can normally be reached Monday to Thursday, 8:30 to 17:30 EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez, can be reached on (571)270-1435. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WALTER H SWANSON/Primary Examiner, Art Unit 2815
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Prosecution Timeline

May 09, 2023
Application Filed
Oct 08, 2025
Non-Final Rejection — §103, §112
Dec 22, 2025
Interview Requested
Jan 07, 2026
Applicant Interview (Telephonic)
Jan 07, 2026
Examiner Interview Summary
Jan 08, 2026
Response Filed
Jan 24, 2026
Final Rejection — §103, §112
Apr 10, 2026
Request for Continued Examination
Apr 11, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
75%
Grant Probability
85%
With Interview (+10.2%)
2y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 815 resolved cases by this examiner. Grant probability derived from career allow rate.

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