DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed on 23 February 2026, with respect to claims 1, 4, and 5 have been fully considered and are persuasive. The 35 U.S.C. § 102 rejection of claims 1, 4, and 5 has been withdrawn. However, upon further considerations, the examiner finds that claims 1, 4 and 5 are rejected under 35 U.S.C. § 103 using Sakurai in view of Lim. Please see rejection below for details.
Applicant's arguments filed on 23 February 2026, with respect to claims 2, 16, and 19 and claims 10-12, 17 and 18 have been fully considered but they are not persuasive. On pages 8 and 9 of the Remarks, the applicant argues that Lim and/or Cheng does not teach the limitations of “wherein at least one of the one of or more slots extend vertically through an opening of the stiffener.” The examiner respectfully disagrees and finds that Lim teaches this limitation. Please see the 35 U.S.C. § 103 rejections of claims 1, 2, 10, and 16 below that describes how Lim teaches these limitations.
The applicant further argues that Cheng does not teach the amended limitations and hence various claims such as claims 10-12, 17, and 18 are patentable. The examiner finds this argument moot due to the reason in the preceding paragraph.
In summary, this application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s)1-2, 4-5, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) as applied to claim 1 above, and further in view of Lim (US 8,598,698 B1).
Regarding claim 1, Sakurai teaches the semiconductor package, comprising:
a first substrate (20) having a top surface (top surface of 20) and a bottom surface (bottom surface of 20); and
a second substrate (10) having a top surface (top surface of 10) and a bottom surface (bottom surface of 10), wherein:
the bottom surface of the first substrate is connected to the top surface of the second substrate via at least one bonding layer (31 & 34; see ¶ [0045]);
the first substrate includes one or more electrically conductive components (23a) arranged on the bottom surface of the first substrate in a first pattern (23a are arranged in a horizontal pattern, see Fig. 1);
the second substrate includes one or more slots (14; see ¶ [0027]) arranged on the bottom surface (14 are found on the bottom surface of 20) of the second substrate in a second pattern (14 are arranged in a horizontal pattern, see Fig. 1),
the one or more slots are each plated (see ¶ [0035]) with an electrically conductive material (12);
the arrangement of the one or more electrically conductive components in the first pattern is aligned with the arrangement of the one or more slots in the second pattern (Fig. 1 shows the outermost 23as are vertically aligned with each 12).
However, Sakurai does not teach the semiconductor package wherein the second substrate includes a stiffener disposed within the second substrate and, wherein at least one of the one or more slots extend through an opening of the stiffener.
Lim, in the same field of invention, teaches a semiconductor package having a substrate (300; see Col. 4 Ln. 21; this is analogous to Sakurai’s second substrate) includes a stiffener (330; see Fig. 3A) disposed within the second substrate,
wherein at least one of the one or more slots (315, see Figs. 3 & 4A; Col. 4 Ln. 52-55: 315 is a through-hole that is drilled through core layer 320, emphasis added) extend through an opening (central area of core layer 320 of substrate that is not occupied by stiffener 330; see Figs. 3A & 4A and Col. 5, Ln: 30-31 “stiffener 330A surrounds the perimeter of core layer 320A”) of the stiffener (Fig. 3A shows slots 315 extending vertically in a portion of the core layer 320, wherein this portion is an opening of the stiffener 330, as shown in Fig. 4).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lim into the device of Sakurai to add a stiffener within the second substrate, wherein the one or more slots in the second substrate extend through an opening of the stiffener. The ordinary artisan would have been motivated to modify Sakurai in the manner set forth above for at least the purpose of using the stiffener to provide increased stability to the second substrate, noting that Sakurai teaches using the second substrate to mount the first substrate and several other devices and hence will have greater mechanical stress due to their added weight, and for the further purpose of reducing the space requirements if the stiffener was placed outside of the second substrate (Lim Background and Col. 4, Ln 8-11), allowing other components to be placed in the package (Lim Col. 4, 11-15). Furthermore, the ordinary artisan is motivated to place the stiffener at the perimeter of the substrate to allow more space of the central portion of the substrate for adding more through-vias (Lim Col. 5, Ln. 26-40). The ordinary skilled artisan would also be motivated to use the slots in the second substrate as a means to connect signals from one end of the second substrate to another end of the second substrate (Lim Col. 4, Ln. 52-57).
Regarding claim 2, the semiconductor package of claim 1, wherein
the stiffener is disposed within the second substrate and is aligned with a perimeter portion (outer edges of the 300, see Lim Fig. 4A; note: 320A is a core layer of substrate 300) of the second substrate, and is not aligned with a central portion of the second substrate (Fig 4A shows 330 not in the central portion of 300), and
the one or more slots (315) are arranged on the bottom surface of the second substrate and are aligned with the central portion of the second substrate (Fig. 4A shows 315 are in the central portion of 300), and are not aligned with the perimeter portion of the second substrate (Fig. 4A shows 315 are not found in the outer edges of 300).
Regarding claim 4, the semiconductor package of claim 1, wherein each of the one or more electrically conductive components of the first substrate and the electrically conductive material of the one or more slots comprises at least copper (Sakurai ¶ [0043]: 23 is made of copper; ¶ [0035]: 12 is formed by copper plating).
Regarding claim 5, the semiconductor package of claim 1, wherein a semiconductor device (E2; see Sakurai Fig. 1) is disposed on the top surface of the first substrate.
Regarding claim 16, Sakurai teaches a semiconductor package, comprising:
a first substrate (20) having a top surface and a bottom surface; and
a second substrate (10) having a top surface and a bottom surface, wherein:
the bottom surface of the first substrate is connected to the top surface of the second substrate via at least one bonding layer (31 & 34, ¶ 0045);
the second substrate includes one or more slots (14, ¶ 0027) on the bottom surface of the second substrate (14 are found on the bottom surface of 20) that are each plated (¶ 0035) with an electrically conductive material (copper).
However, Sakurai does not teach: the second substrate includes a stiffener disposed within the second substrate, wherein at least one of the one or more slots extend vertically through an opening of the stiffener.
Lim, in the same field of invention, teaches a device wherein the second substrate (300) includes a stiffener (330) disposed within the second substrate,
wherein at least one of the one or more slots (315, see Figs. 3A & 4A; Col. 4 Ln. 52-55: 315 is a through-hole that is drilled through core layer 320, emphasis added) extend vertically through an opening (central area of core layer 320 of substrate that is not occupied by stiffener 330; see Figs. 3A & 4A and Col. 5, Ln: 30-31 “stiffener 330A surrounds the perimeter of core layer 320A”) of the stiffener (Fig. 3 shows slots 315 extending vertically in a portion of the core layer 320, wherein this portion is an opening of the stiffener 330, as shown in Fig. 4).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lim into the device of Sakurai to dispose a stiffener within the second substrate, wherein at least one of the one or more slots extend vertically through an opening of the stiffener. The ordinary artisan would have been motivated to modify Sakurai in the manner set forth above for at least the purpose of using the stiffener to provide increased stability to the second substrate, noting that Sakurai teaches using the second substrate to mount the first substrate and several other devices and hence will have greater mechanical stress, and for the further purpose of reducing the space requirements if the stiffener was placed outside of the second substrate (Lim Background and Col. 4, Ln 8-11), allowing other components to be placed in the package (Lim Col. 4, 11-15). Furthermore, the ordinary artisan is motivated to place the stiffener at the perimeter of the substrate to allow more space of the central portion of the substrate for adding more through-vias (Lim Col. 5, Ln. 26-40). The ordinary skilled artisan would also be motivated to use the slots in the second substrate as a means to connect signals from one end of the second substrate to another end of the second substrate (Lim Col. 4, Ln. 52-57).
Regarding claim 19, the semiconductor package of claim 16, wherein:
the first substrate includes one or more electrically conductive components (23a, see Sakurai Fig. 1): on the bottom surface of the first substrate that are electrically connected (through 31) to the one or more slots of the second substrate.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) as applied to claim 1 above, and further in view of Cheng (US 2022/0068840 A1)
Regarding claim 3, Sakurai teaches semiconductor package of claim 1, and further teaches the first substrate comprising of a first redistribution layer (layer below 21) made of insulating layers (24; ¶ [0043]: 24 is a solder resist layer) and metal layers (27: ¶ [0048]: made of copper), the second substrate comprising of a second redistribution layer (layer on top of 11) made of insulating layers (13: ¶ [0031]: 13 is a solder resist layer made of epoxy resin) and metal layers (12a; ¶ [0028]: 12a made of copper), and the at least one bonding layer (31 & 34, ¶ [0045]) comprising of a solder ball (¶ [0045]) between the first redistribution layer and second redistribution layer and a gap between the first redistribution layer and second redistribution layer (Fig. 1: gap is made due to the solder balls).
However, Sakurai does not teach: wherein the bottom surface of the first substrate and the top surface of the second substrate are laminated together via the at least one bonding layer.
Cheng, in the same field of invention, teaches a device wherein the bottom surface (bottom surface of 20) of the first substrate (20) and the top surface (top surface of 10 & 40) of the second substrate (10 & 40) are laminated (¶ [0034]: “the binding layer 30 may include a non-conductive film (NCF), and the NCF may be laminated on the encapsulant 40”) together via the at least one bonding layer (30).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cheng into the device of Sakurai laminate together the bottom surface of the first substrate and the top surface of the second substrate via at least one bonding layer. The ordinary artisan would have been motivated to modify Sakurai in the manner set forth above for using the laminated bonding layer (30; Cheng ¶ [0003], ¶ [0023]) to reduce the warpage around the gap (see the gap in Sakurai Fig. 1) between stacked structures (Cheng ¶ [0002]) that are composed of the first substrate having a first redistribution layer (22, Cheng ¶ [0018]) and the second substrate having a second redistribution layer (12, Cheng ¶ [0017]; metal layer 12 surrounded by epoxy resin), due to a characteristic mismatch between layers (Cheng ¶ [0002]) during high temperature operations such as reflow and baking processing steps (Cheng ¶ [0002]).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) in view of Lim (US 8,598,698 B1) as applied to claim 1 above, and further in view of Kawai (US 2021/0183759 A1).
Regarding claim 6, Sakurai et al. teach the semiconductor package of claim 1, but do not teach: wherein the bottom surface of the first substrate does not extend to be over a portion of the top surface of the second substrate.
Kawai, in the same field of invention, teaches a semiconductor package (100, see Fig. 2) wherein the bottom surface (bottom surface of 30) of the first substrate (30) does not extend to be over a portion (portion of the top surface of 10 directly adjacent to 20) of the top surface of the second substrate (10).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kawai into the semiconductor package of Sakurai et al. to not extend the bottom surface of the first substrate over a portion of the top surface of the second substrate. The ordinary artisan would have been motivated to modify Sakurai et al. in the manner set forth above for at least the purpose of using the portion where the bottom surface of the first substrate does not extend over the top surface of the second substrate to mount a power source (20, see Kawai ¶ [0031]) to provide power to an electronic component (50) that is mounted on top of the second substrate (Kawai ¶ [0037]).
Regarding claim 7, the semiconductor package of claim 6, wherein at least one power supply component (20, see Kawaii Fig. 2) is disposed on the portion of the top surface of the second substrate.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) in view of Lim (US 8,598,698 B1) as applied to claim 1 above, and further in view of Jain (US 2018/0115356 A1).
Regarding claim 8, Sakurai et al. teach the semiconductor package of claim 1, and further teach: using conductor layers (15,16) of the second substrate to release heat (¶ [0048]), with the conductor layers connected to a wiring board (40, see Fig. 1 and ¶ [0058]).
However, Sakurai et al. do not teach: comprising a heatsink disposed on the bottom surface of the second substrate.
Jain, in the same field of invention, teaches a device comprising a heatsink (24, see Fig. 2) disposed on the bottom surface of the second substrate (16; Sakurai in view of Jain teaches 16 to be the second substrate, see below).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Jain into the device of Sakurai et al. to dispose a heatsink on the bottom surface of the second substrate. The ordinary artisan would have been motivated to modify Sakurai et al. in the manner set forth above for at least the purpose of routing the heat generated by devices (E1/E2, see Sakurai Fig. 1), which is routed away from the devices through the wiring conductors (15,16) and into the wiring board (40), out and away from the wiring board (Jain ¶ [0037]), thereby making both the wiring board of Sakurai et al. and the heat sink of Jain collectively act as a heat sink disposed on the bottom surface of the second substrate (see also Jain Fig. 2, where heat sink 24 is disposed below wiring board 18) and for the further purpose of avoiding performance degradation of the device due to unwanted heat (Jain ¶ [0037]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) in view of Lim (US 8,598,698 B1) as applied to claim 1 above, and further in view of Okamoto (US 2018/0138141 A1).
Regarding claim 9, Sakurai et al. teach the semiconductor package of claim 1, and further teach the device
wherein the first substrate comprises a first set of materials (¶ [0043]: 21 made of thermosetting resin containing glass cloth) and the second substrate comprises a second set of materials (¶ [0027]:11 made of thermosetting resin containing glass cloth),
wherein the first set of materials and the second set of materials are the same.
Sakurai further teaches the first substrate and the second substrates are wiring substrates (¶ [0027], ¶ [0043]).
However, Sakurai et al. does not teach the semiconductor package wherein the first set of materials and the second set of materials are different.
Okamoto, in the same field of invention, teaches a semiconductor package wherein the first set of materials and the second set of materials can be the same or can be different (¶ [0046]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Okamoto into the semiconductor package of Sakurai et al. to have different set of first materials and second materials that comprise the first substrate and second substrate, respectively. The ordinary artisan would have been motivated to modify Sakurai et al. in the manner set forth above for at least the purpose of substituting different materials that are known in the art for making wiring substrates for semiconductor packages (Okamoto ¶ [0046]).
Claim(s) 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) and further in view of Lim (US 8,598,698 B1) and Cheng (US 2022/0068840 A1).
Regarding claim 10, Sakurai teaches a semiconductor package, comprising:
a first substrate (20) having a top surface (top surface of 20) and a bottom surface (bottom surface of 20); and
a second substrate (10) having a top surface (top surface of 10) and a bottom surface (bottom surface of 10), wherein:
the bottom surface of the first substrate is connected to the top surface of the second substrate via at least one bonding layer (31 & 34, ¶ 0045);
the second substrate includes one or more slots (14, ¶ 0027) on the bottom surface of the second substrate (14 are found on the bottom surface of 20),
wherein each slot, of the one or more slots, extends through the second substrate (see Fig. 1);
the one or more slots are each plated (¶ 0035) with an electrically conductive material (copper).
However, Sakurai does not teach the second substrate includes a stiffener disposed within the second substrate, wherein at least one of the one or more slots extend vertically through an opening of the stiffener.
Lim, in the same field of invention, teaches a device wherein the second substrate (300) includes a stiffener (330) disposed within the second substrate,
wherein at least one of the one or more slots (315, see Figs. 3A & 4A; Col. 4 Ln. 52-55: 315 is a through-hole that is drilled through core layer 320, emphasis added) extend vertically through an opening (central area of core layer 320 of substrate that is not occupied by stiffener 330; see Figs. 3A & 4A and Col. 5, Ln: 30-31 “stiffener 330A surrounds the perimeter of core layer 320A”) of the stiffener (Fig. 3 shows slots 315 extending vertically in a portion of the core layer 320, wherein this portion is an opening of the stiffener 330, as shown in Fig. 4).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lim into the device of Sakurai to dispose a stiffener with the second substrate, wherein the one or more slots in the second substrate extend through an opening of the stiffener. The ordinary artisan would have been motivated to modify Sakurai in the manner set forth above for at least the purpose of using the stiffener to provide increased stability to the second substrate, noting that Sakurai teaches using the second substrate to mount the first substrate and several other devices and hence will have greater mechanical stress, due to their added weight, and for the further purpose of reducing the space requirements if the stiffener was placed outside of the second substrate (Lim Background; Col. 4, Ln 8-11), allowing other components to be placed in the package (Lim Col. 4, 11-15). Furthermore, the ordinary skilled artisan would have been motivated to have the slots in the second substrate extend vertically through an opening of the stiffener. The ordinary skilled artisan would also be motivated to use the slots in the second substrate as a means to connect signals from one end of the second substrate to another end of the second substrate (Lim Col. 4, Ln. 52-57).
Sakurai further teaches the first substrate comprising of a first redistribution layer (layer below 21) made of insulating layers (24; ¶ [0043]: 24 is a solder resist layer) and metal layers (27: ¶ [0048]: made of copper), the second substrate comprising of a second redistribution layer (layer on top of 11) made of insulating layers (13: ¶ [0031]: 13 is a solder resist layer made of epoxy resin) and metal layers (12a; ¶ [0028]: 12a made of copper), and the at least one bonding layer (31 & 34, ¶ [0045]) comprising of a solder ball (¶ [0045]) between the first redistribution layer and second redistribution layer and a gap between the first redistribution layer and second redistribution layer (Fig. 1: gap is made due to the solder balls).
However, Sakurai does not teach wherein each slot, of the one or more slots, extends through the at least one bonding layer.
Cheng, in the same field of invention, teaches a device wherein each slot (slot occupied by via 24; see Fig. 1A and ¶ [0020]), of the one or more slots, extends through the at least one bonding layer (30 & 14 & 40).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cheng into the device of Sakura in view of Lim to extend the each slot through the at least one bonding layer. The ordinary artisan would have been motivated to modify Sakura in view of Lim in the manner set forth above for using an additional bonding layer (30 & 40; Cheng ¶ [0003], ¶ [0023]) to reduce the warpage around the empty gap (see gap in Sakurai Fig. 1) between stacked structures (Cheng ¶ [0002]) that are composed of a first substrate having a first redistribution layer (22, Cheng ¶ [0018]) and a second substrate having a second redistribution layer (12, Cheng ¶ [0017]; metal layer 12 surrounded by epoxy resin), due to a characteristic mismatch between layers (Cheng ¶ [0002]) during high temperature operations such as reflow and baking processing steps (Cheng ¶ [0002]). Using the additional bonding layer requires the via (24, Cheng ¶ [0020]) and its slot to extend through the bonding layer in order maintain electrical connection between the first and second substrate (Cheng ¶ [0020]).
Regarding claim 11, the semiconductor package of claim 10, wherein:
the stiffener is disposed within the second substrate and is aligned with a perimeter (Lim Fig. 4A shows stiffener 330 disposed on the outer edges of substrate 300) portion of the second substrate, and
the one or more slots are arranged on the bottom surface of the second substrate (Sakurai Fig. 1 shows slots 14 are found on the bottom surface of substrate 10) and are aligned with a central portion of the second substrate (Lim Fig. 4A shows the slots occupied by vias 315 are in the central portion of 300).
Regarding claim 12, the semiconductor package of claim 10, wherein:
the first substrate includes one or more electrically conductive components (23a, see Sakurai Fig. 1) on the bottom surface of the first substrate that are aligned with the one or more slots on the bottom surface of the second substrate (Fig. 1 shows two outermost 23a on the left and right side are vertically aligned with each 12).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) in view of Lim (US 8,598,698 B1) and Cheng (US 2022/0068840 A1) as applied to claim 10 above, and further in view of Kawai (US 2021/0183759 A1).
Regarding claim 13, Sakurai et al. teach the semiconductor package of claim 10, but do not teach: wherein the bottom surface of the first substrate does not extend to be over a portion of the top surface of the second substrate.
Kawai, in the same field of invention, teaches a semiconductor package (100, see Fig. 2) wherein the bottom surface (bottom surface of 30) of the first substrate (30) does not extend to be over a portion (portion of the top surface of 10 directly adjacent to 20) of the top surface of the second substrate (10).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kawai into the semiconductor package of Sakurai et al. to not extend the bottom surface of the first substrate over a portion of the top surface of the second substrate. The ordinary artisan would have been motivated to modify Sakurai et al. in the manner set forth above for at least the purpose of using the portion where the bottom surface of the first substrate does not extend over the top surface of the second substrate to mount a power source (20, see Kawai ¶ [0031]) to provide power to an electronic component (50) that is mounted on top of the second substrate (Kawai ¶ [0037]).
Regarding claim 14, the semiconductor package of claim 13, wherein at least one power supply component (20, see Kawaii Fig. 2) is disposed on the portion of the top surface of the second substrate.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) and in view of Lim (US 8,598,698 B1) and Cheng (US 2022/0068840 A1) as applied to claim 10 above and further in view of Jain (US 2018/0115356 A1).
Regarding claim 15, Sakurai in view of Lim and Cheng teaches the semiconductor package of claim 10, but does not teach a device further comprising a heatsink disposed on the bottom surface of the second substrate.
Jain, in the same field of invention, teaches a device comprising a heatsink (24) disposed on the second substrate (16; Sakurai in view of Lim and Jain teaches 16 to be the second substrate, see below).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Jain into the device of Sakurai in view of Lim and Cheng to dispose a heatsink on the bottom surface of the second substrate.
The ordinary artisan would have been motivated to modify Sakurai in view of Lim and Cheng in the manner set forth above for at least the purpose of routing the heat generated that is routed away from the devices (E1/E2) of Sakurai through the wiring conductors (15,16) and into the wiring board (40) out and away from the wiring board (Jain ¶ 0037), thereby making both the wiring board of Sakurai and the heat sink of Jain collectively act as a heat sink disposed on the bottom surface of the second substrate (see also Jain Fig. 2) and for the further purpose of avoiding performance degradation of the device due to unwanted heat (Jain ¶ 0037).
Claim(s) 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) in view of Lim (US 8,598,698 B1) as applied to claim 16 above, and further in view of Cheng (US 2022/0068840 A1).
Regarding claim 17, Sakurai in view of Lim teaches semiconductor package of claim 16, wherein each slot, of the one or more slots, extends through the second substrate (see Sakurai Fig. 1).
Sakurai further teaches the first substrate comprising of a first redistribution layer (layer below 21) made of insulating layers (24; ¶ [0043]: 24 is a solder resist layer) and metal layers (27: ¶ [0048]: made of copper), the second substrate comprising of a second redistribution layer (layer on top of 11) made of insulating layers (13: ¶ [0031]: 13 is a solder resist layer made of epoxy resin) and metal layers (12a; ¶ [0028]: 12a made of copper), and at least one bonding layer (31 & 34, ¶ [0045]) comprising of a solder ball (¶ [0045]) between the first redistribution layer and second redistribution layer and a gap between the first redistribution layer and second redistribution layer (Fig. 1: gap is made due to the solder balls).
However, Sakurai does not teach wherein each slot, of the one or more slots, extends through the at least one bonding layer.
Cheng, in the same field of invention, teaches a device wherein each slot (the slot occupied by via 24; ¶ [0020]), of the one or more slots, extends through the at least one bonding layer (30 & 14 & 40).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cheng into the device of Sakura in view of Lim to extend the each slot through the at least one bonding layer. The ordinary artisan would have been motivated to modify Sakura in view of Lim in the manner set forth above for using an additional bonding layer (30 & 40; Cheng ¶ [0003], ¶ [0023]) to reduce the warpage around the gap (see Sakurai Fig. 1) between stacked structures (Cheng ¶ [0002]) that are composed of a first substrate having a first redistribution layer (22, Cheng ¶ 0018) and a second substrate having a second redistribution layer (12, Cheng ¶ [0017]; metal layer 12 surrounded by epoxy resin), due to a characteristic mismatch between layers (Cheng ¶ [0002]) during high temperature operations such as reflow and baking processing steps (Cheng ¶ [0002]). Using the additional bonding layer requires the via (24, Cheng ¶ [0020]) and its slot to extend through the bonding layer in order maintain electrical connection between the first and second substrate.
Regarding claim 18, the semiconductor package of claim 17, wherein the stiffener has an opening (Lim Fig. 4: central portion of the substrate 300) and at least one slot, of the one or more slots, extends through the opening of the stiffener (Lim Fig. 4 shows slots of vias 315 in the central portion of the substrate 300).
Claim 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakurai ( US 2016/0095218 A1) in view of Lim (US 8,598,698 B1) as applied to claim 16 above and further in view of Jain (US 2018/0115356 A1).
Regarding claim 20, Sakurai in view of Lim semiconductor package of claim 16, further teaches using conductor layers (15,16; see Sakurai Fig. 1) of the second substrate to release heat (Sakurai ¶ [0048]), with the conductor layers connected to a wiring board (40, see Fig. 1 and ¶ [0058]).
However, Sakurai in view of Lim does not teach: further comprising a heatsink disposed on the second substrate.
Jain, in the same field of invention, teaches a device comprising a heatsink (24) disposed on the second substrate (16; Sakurai in view of Lim and Jain teaches 16 to be the second substrate, see below).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Jain into the device of Sakurai in view of Lim to dispose a heatsink on the bottom surface of the second substrate.
The ordinary artisan would have been motivated to modify Sakurai in view of Lim in the manner set forth above for at least the purpose of routing the heat generated that is routed away from the devices (E1/E2) of Sakurai through the wiring conductors (15,16) and into the wiring board (40) out and away from the wiring board (Jain ¶ [0037]), thereby making both the wiring board of Sakurai and the heat sink of Jain collectively act as a heat sink disposed on the bottom surface of the second substrate (see also Jain Fig. 2) and for the further purpose of avoiding performance degradation of the device due to unwanted heat (Jain ¶ [0037]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899