Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
New claims 19-20 have been added. Currently, claims 1-6 and 19-20 are pending, and claims 7-18 have been withdrawn from further consideration.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Oosuka et al. (Pub. No. US 2009/0108379 A1, herein Oosuka) in view of Lee et al. (Pub. No. US 2019/0288066 A1, herein Lee).
Regarding claim 1, Oosuka discloses an integrated structure of semiconductor devices having a shared contact plug 63, comprising: a first device including a first gate, wherein the first gate has a conduction region 42, two spacer regions 44-45 and a protection region 46, wherein the two spacer regions overlay and are connected with two lateral sides of the conductive region, respectively, wherein one of the lateral sides is a shared side and wherein the protection region overlays and is connected with one of the two spacer regions which is located at the shared side of the conductive region (Oosuka: Figs. 1, 6, 9 and paragraphs [0030], [0035], [0057]); a second device 12 including a shared region 29A, wherein the shared region is located in a semiconductor layer 18 which is located below and outside the protection region; and a shared contact plug 63 formed on and in contact with the conductive region and the shared region, wherein the first gate is electrically connected to the shared region via the shared contact plug; wherein the shared contact plug overlays and is connected with the protection region (Oosuka: Figs. 1, 6, 9 and paragraphs [0030]-[0031], [0057]-[0058]).
Oosuka does not specifically show wherein the protection region is only formed at the shared side.
However, in the same field of endeavor, Lee shows an integrated structure of semiconductor devices, comprising: a device including a first gate, wherein the first gate has a conduction region 300 ([0054]), two spacer regions 330 ([0058]) and a protection region 600 ([0054), wherein the two spacer regions overlay and are connected with two lateral sides of the conductive region, respectively, wherein one of the lateral sides is a shared side and wherein the protection region overlays and is connected with one of the two spacer regions which is located at the shared side of the conductive region (Figs. 2, 6), wherein the protection region is only formed at the shared side to prevent the silicon atoms from formation of the silicide layer on a surface of the substrate or the gate electrode (Figs. 2, 6 and [0061]-[0062]).
Therefore, given the teachings of Lee, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Oosuka in view of Lee by employing the protection region only at the shared side.
Regarding claim 4, Oosuka in view of Lee teaches the integrated structure of semiconductor devices having a shared contact plug as claimed in claim 1, wherein a length of the protection region is 1/2-fold to 1/3-fold of a length of the shared contact plug (Oosuka: Figs. 1, 6, 9 and paragraphs [0040], [0047]).
Regarding claim 5, Oosuka in view of Lee teaches the integrated structure of semiconductor devices having a shared contact plug as claimed in claim 1, further comprising: a contact etch stop layer (CESL) 71, which is formed on the conduction region, the two spacer regions and the protection region (Oosuka: Figs. 1, 6, 9 and paragraphs [0036]-[0037]).
The limitation "wherein the CESL serves to function as an etch stop layer in an etching process step for forming the shared contact plug" is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is taught by the reference even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 6, Oosuka in view of Lee teaches the integrated structure of semiconductor devices having a shared contact plug as claimed in claim 1, wherein the first device and the second device are two metal oxide semiconductor (MOS) devices which are cross-coupling to each other in a static random access memory (SRAM) (Oosuka: Figs. 1, 6, 9 and paragraphs [0006], [0011]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Oosuka in view of Lee, as applied above, and further in view of Li (Pub. No. US 2016/0190335 A1).
Regarding claim 2, The previous combination does not specifically state a high voltage device, wherein the high voltage device includes a split gate, wherein the split gate has a field oxide region.
However, Li in the same field of endeavor, shows a similar configuration as Oosuka (MIS transistor and memory cell) comprising: a high voltage device, wherein the high voltage device includes a split gate, wherein the split gate has a field oxide region to improve the erasure ability, reliability and durability (Li: Fig. 18 and paragraphs [0006]-[0009], [0019], [0027]).
Therefore, given the teachings of Li, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Oosuka in view of Li by employing the shared contact plug of Oosuka in Li’s device to benefit from both the use of the local interconnect structure, not only the reduction in wiring resistance but also reduction in the size of the memory cell, as well as the improvement in erasure ability.
The limitation "wherein the protection region and the field oxide region are formed by one same deposition process step and one same patterning process step" is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is taught by the reference even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Oosuka in view of Lee, as applied above, and further in view of Tsao et al. (U.S. Pat. No. 6,137,144, herein Tsao).
Regarding claim 3, the previous combination does not specifically state a high voltage device, wherein the high voltage device includes a silicide alignment block (SAB) oxide region.
However, in column 2 lines 12-42, Tsao states “one of the current methods of meeting this goal is through a split gate CMOS process. In this process, the high voltage transistors will have a thicker gate oxide, while typically having lower channel dopings and lower, less abrupt source/drain dopings. One of the problems with this solution is that there is a significantly reduced margin in the high-voltage ESD protection…a number of solutions to this problem, such as separate source/drain patterns and implants, separate ESD patterns and implants, use of a silicide block pattern/process, or increasing epi thickness would result in significant cost additions. Other methods can be applied but would result in decreased performance, such as reduced SALICIDE thickness. Another option is to reduce the channel length only, but here the transistor would be constrained by off-state leakage requirements”.
Therefore, given the teachings of Tsao, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Oosuka in view of Tsao by employing the known technique of SAB.
The limitation "wherein the protection region and the SAB oxide region are formed by one same deposition process step and one same patterning process step" is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is taught by the reference even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Allowable Subject Matter
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
With respect to claim 19, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the protection region includes a top surface, and wherein the shared contact plug entirely covers the top surface of the protection region.
With respect to claim 20, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, further comprising an insulation structure in the semiconductor layer, wherein, in a vertical direction, the protection region is located between the insulation structure and the shared contact plug.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1-6 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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July 6, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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