DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 10, 2023, May 15, 2024 is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Device embodiment 1 (claims 1-9 and 19-20) in the reply filed on January 6, 2026 is acknowledged.
Claims 10-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected device embodiment, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 6, 2026.
Claim Objections
Claim 4 is objected to because of the following informalities: line 3 recites the limitation “a layer of a second insulator material at the first face of the support structure”. Examiner believes this is meant to be at the second face as the second insulator is meant to contain the second doped region which is formed at the second face. For purposes of examination his will be interpreted as “a layer of a second insulator material at the second face of the support structure” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 19-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 3 recites the limitation: “where an individual transistor includes” it is unclear if the individual transistor is meant to be a subsect of the one or more transistors or if the individual transistor is separate from that set. For purposes of examination this will be interpreted as “where an individual transistor of the one or more transistors…”
Claim 5 recites the limitation "the gate of the first transistor" and “the gate of the second transistor” in lines 3-5. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination his will be interpreted as “a gate of the first transistor” and “a gate of the second transistor.
Claim 5 recites the limitation "the second doped region of the first transistor" and “the second doped region of the second transistor” in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination his will be interpreted as "a second doped region of the first transistor" and “a second doped region of the second transistor”
Claim 19, line 3 recites the limitation: “each transistor having” it is unclear if the each transistor is meant to be a subsect of the plurality of transistors or if the each transistor is separate from that set. For purposes of examination this will be interpreted as “each transistor of the plurality of transistors…”
Claim 19 recites the limitation "the transistor" in line 6. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination his will be interpreted as “each transistor”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Colinge (US 2015/0372149).
Claim 1, Colinge discloses (Fig. 2) an integrated circuit (IC) device, comprising: a support structure (104, first inter-layer dielectric layer, Para [0021]) having a first face (top surface face, hereinafter “f1”) and an opposing second face (bottom surface face, hereinafter “f2”); and one or more transistors (101/201, nanowires of vertical transistors, Para [0025]), where an individual transistor (201) of the one or more transistors includes: a channel structure (214, channel region, Para [0026]) comprising a semiconductor material (214 has p-type semiconductor, Para [0045]) and extending between the first face and the second face of the support structure (214 extends between f1 and f2), a gate (203, gate structure, Para [0027]) comprising a gate electrode material (222/232/234, gate metal layer/first workfunction metal layer/second workfunction metal layer, Para [0027], hereinafter “electrode”) at least partially wrapping around the channel structure (electrode partially wraps around a section of 214) and surrounded by the support structure (electrode is surrounded by 104), a first doped region (216, second drain/source region comprising p-doped region, Para [0040]) adjacent a portion of the channel structure at the first face of the support structure (216 is adjacent to 214 at f1 of 104), and a second doped region (212, first drain/source region comprising p-doped region, Para [0039]) adjacent a portion of the channel structure at the second face of the support structure (212 is adjacent to 214 at f2 of 104).
Claim 3, Colinge discloses (Fig. 2) the IC device according to claim 1, wherein the gate (203) of the individual transistor (201) further includes a gate insulator material (206, gate dielectric layer, Para [0029]) at least partially wrapping around the channel structure (206 partially wraps around a section of 214), wherein the gate insulator material is between the channel structure and the gate electrode material (206 is between 214 and electrode). Claim(s) 1-3, 5-8, 19-20 and 22-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jezewski (US 2020/0219804).
Claim 1, Jezewski discloses (Figs. 5A-5O) an integrated circuit (IC) device, comprising: a support structure (Fig. 5K, 512, ILD, Para [0041]) having a first face (bottom surface face of 512, hereinafter “f1”) and an opposing second face (top surface face of 512, hereinafter “f2”); and one or more transistors (Fig. 5K, plurality of 516/526/530, gate/source/drain, Para [0052] –[0057], hereinafter “transistor”), where an individual transistor (left transistor) of the one or more transistors includes: a channel structure (524, TMD structure which is active channel structure material, Para [0018], [0049] comprising a semiconductor material (TMD may be active semiconductor, Para [0018] – [0119]) and extending between the first face and the second face of the support structure (Fig. 5K, 524 extends between f1 and f2 of 512), a gate (Fig. 5J, 520/516A, gate dielectric/gate electrode, Para [0047]), comprising a gate electrode material (516A) at least partially wrapping around the channel structure (Fig. 5K, 516A partially wraps around a portion of 524) and surrounded by the support structure (516A is surrounded by 512), a first doped region (526, bottom contact structure which may comprise source/drain region which would be doped, Para [0057]) adjacent a portion of the channel structure at the first face of the support structure (526 is adjacent a portion of 524 at f1 of 512), and a second doped region (530, top contact structure which may comprise source/drain region which would be doped, Para [0057]) adjacent a portion of the channel structure at the second face of the support structure (530 is adjacent a portion of 524 at f2 of 512). Claim 2, Jezewski discloses (Figs. 5A-5O) the IC device according to claim 1, wherein the channel structure (524) has a shape of a nanoribbon extending substantially vertically through (524 is through 512) the support structure (the device may include nanoribbons as part of the gate-all-around configuration, Para [0029]). Claim 3, Jezewski discloses (Figs. 5A-5O) the IC device according to claim 1, wherein the gate (520/516A) of the individual transistor (left transistor) further includes a gate insulator material (520) at least partially wrapping around the channel structure (520 would partially wrap around a portion of 524), wherein the gate insulator material is between the channel structure and the gate electrode material (520 is between 524 and 516A). Claim 5, Jezewski discloses (Figs. 5A-5O) the IC device according to claim 1, wherein: the one or more transistors (transistor) include a first transistor (left transistor) and a second transistor (right transistor), and the IC device further includes a conductive line (Fig. 5O, 536c/536d, interconnects, Para [0060]) having a first portion (536c) in contact with a gate (516A, gate electrode, Para [0060]) of the first transistor (left transistor) and having a second portion (536d) in contact with a gate (516B, gate electrode, Para [0060]) of the second transistor (right transistor). Claim 6, Jezewski discloses (Figs. 5A-5O) the IC device according to claim 5, wherein the conductive line (536c/536d) is substantially parallel to the support structure (as shown in Fig. 5O a horizontal portion of 526c/536d is parallel to 512) and is closer to the second face of the support structure than to the first face of the support structure (536c/536d is closer to f2 than to f1 of 512). Claim 7, Jezewski discloses (Figs. 5A-5O) the IC device according to claim 5, wherein: the conductive line (536c/536d) is a first conductive line (536c/536d are interconnects), and the IC device further includes a second conductive line (536a, interconnect, Para [0060]) having a first portion (left portion of 536a) in contact with a second doped region (left 530) of the first transistor (left portion of 536a is in contact with left 530 of left transistor) and having a second portion (right portion of 536a) in contact with a second doped region (right 530) of the second transistor (right portion of 536a is in contact with right 530 of right transistor). Claim 8, Jezewski discloses (Figs. 5A-5O) the IC device according to claim 7, wherein the conductive line (536c/536d) is substantially parallel to the support structure (as shown in Fig. 5O a horizontal portion of 526c/536d is parallel to 512) and is closer to the second face of the support structure than to the first face of the support structure (536c/536d is closer to f2 than to f1 of 512). Claim 19, Jezewski discloses (Figs. 1 and 5M-5O) an integrated circuit (IC) device, comprising: a substrate (Fig. 5M, 512, ILD structure considered substrate as other elements formed on there, Para [0041]); a logic circuitry (Fig. 1, 101/106, device layer/interconnect may contain logic, Para [0025]) comprising (101/106 comprises transistors which are shown in Figs. 5M-5O, Para [0027]) a plurality of transistors (Fig. 5M, plurality of 516/526/530, gate/source/drain, Para [0052] –[0057], hereinafter “transistor”), each transistor of the plurality of transistors having (both left and right transistor) : a vertical channel region (unlabeled in Fig. 5M, but region between 526 and 530 is vertical channel structure, Para [0056], hereinafter “channel”) extending between a first face of the substrate (top surface face of 512, hereinafter “f1”) and an opposing second face of the substrate (bottom surface of 512, hereinafter “f2”), a first region (Fig. 5M, 530, top contact structure, Para [0057]) of a pair of a source region and a drain region (530 can be used as a source or drain, Para [0057]) of each transistor (left and right transistor) at the first face of the substrate (530 is formed at f1 of 512), and a second region (Fig. 5M, 526, bottom contact structure, Para [0057]) of the pair at the second face of the substrate (526 is formed at f2 of 512); a plurality of first interconnects (Fig. 5O, 536, interconnects connected to 530s and 516, Para [0060]) in contact with the first region of one or more of the plurality of transistors (536s are in electrical contact with 526 of transistor as seen in Fig. 5O); and a plurality of second interconnects (Fig. 5M, Ma, metal lines, Para [0038]) in contact with the second region of one or more of the plurality of transistors (Ma is contact with 526 of transistor), wherein the first interconnects are closer to the first face of the substrate than to the second face of the substrate (Fig. 5O, 536s are closer to f1 of 512 than f2 of 512) and the second interconnects are closer to the second face of the substrate than to the first face of the substrate (Fig. 5O, Ma are closes to f2 of 512 than f1 of 512). Claim 20, Jezewski (Figs. 1 and 5M-5O) the IC device according to claim 19, wherein the logic circuitry includes a two-legged inverter (Fig. 1, 101 shows an inverter device and comprises two sections, Para [0025]). Claim 22, Jezewski (Figs. 1 and 5M-5O) the IC device according to claim 19, wherein the logic circuitry (Fig. 1, 101/106) includes a two-input NAND circuitry (101 can comprises NAND gates and can have any given number of connections, Para [0025]). Claim 23, Jezewski (Figs. 1 and 5M-5O) the IC device according to claim 19, wherein the logic circuitry (Fig. 1, 101/106) includes a two-input NOR circuitry (101 can comprises NOR gates and can have any given number of connections, Para [0025])..
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jezewski (US 2020/0219804) as applied to claim 19 above, and further in view of Ohmaru (US 2015/0295570).
Claim 21, Jezewski discloses the IC device according to claim 19. Jezewski does not explicitly disclose wherein the logic circuitry includes a buffer circuitry. However, Ohmaru discloses (Fig. 1) a logic circuitry which includes a buffer portion (Para [0096] – [0097]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the buffer circuitry of Ohmaru to the logic circuitry of Jezewski as I can have compensate logic levels of input and output signals (Ohmaru, Para [0096] – [0097]).
Allowable Subject Matter
Claims 4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejection above and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Colinge (US 2015/0372149), Jezewski (US 2020/0219804), Ohmaru (US 2015/0295570), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 4, the first doped region is in the layer of the first insulator material and the second doped region is in the layer of the second insulator material.
Regarding Claim 9, a third conductive line having a first portion in contact with the second doped region of the first transistor and having a second portion in contact with the second doped region of the third transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/G.G.R/Examiner, Art Unit 2812