Prosecution Insights
Last updated: August 12, 2026
Application No. 18/314,973

SILICON WAFER AND EPITAXIAL SILICON WAFER

Non-Final OA §103
Filed
May 10, 2023
Priority
May 11, 2022 — JP 2022-078458
Examiner
CHEN, DAVID Z
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SUMCO Corporation
OA Round
3 (Non-Final)
45%
Grant Probability
Moderate
3-4
OA Rounds
4m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
307 granted / 686 resolved
-23.2% vs TC avg
Strong +50% interview lift
Without
With
+49.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
51 currently pending
Career history
753
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.2%
+9.2% vs TC avg
§102
24.7%
-15.3% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 686 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 30, 2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2009/0226737 A1 to Kurita et al. (“Kurita”) in view of JP-2001102384-A to Ninomiya (“Ninomiya”). As to claim 1, although Kurita discloses a p++ silicon wafer (W0) made of monocrystalline silicon, the silicon wafer (W0) containing boron as a dopant and having a resistivity of 1 mΩ·cm or more and 10 mΩ·cm or less, the silicon wafer (W0) having: an oxygen concentration of 14.5×1017 atoms/cm3 or more and 16×1017 atoms/cm3 or less; and a carbon concentration of 5×1017 atoms/cm3 or less, and the silicon wafer (W0) being free from crystal originated particles (COPs) and dislocation clusters (See Fig. 1, ¶ 0012, ¶ 0013, ¶ 0019, ¶ 0036, ¶ 0037, ¶ 0038, ¶ 0040, ¶ 0041, ¶ 0047, ¶ 0048, ¶ 0050, ¶ 0071, ¶ 0084, ¶ 0091, ¶ 0104, ¶ 0113, ¶ 0117), Kurita does not further disclose the carbon concentration of 2×1016 atoms/cm3 or more. However, Ninomiya does disclose the carbon concentration of 2×1016 atoms/cm3 or more (See ¶ 0016, ¶ 0021). In view of the teaching of Ninomiya, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Kurita to have the carbon concentration of 2×1016 atoms/cm3 or more because oxygen precipitation nuclei can be formed uniformly in the crystal growth direction (See ¶ 0016, ¶ 0021). As to claim 6, Kurita in view of Ninomiya further discloses wherein the carbon concentration of the silicon wafer (W0) is 2.58×1016 atoms/cm3 or more (See ¶ 0021). As to claim 7, Kurita in view of Ninomiya further discloses wherein the carbon concentration of the silicon wafer (W0) is 3×1016 atoms/cm3 or more (See ¶ 0021). Claim(s) 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2009/0226737 A1 to Kurita et al. (“Kurita”) and JP-2001102384-A to Ninomiya (“Ninomiya”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2011/0300371 A1 to Omote et al. (“Omote”). The teachings of Kurita and Ninomiya have been discussed above. As to claim 2, although Kurita in view of Ninomiya does not further disclose wherein an epitaxial layer has a resistivity of 1 Ω·cm or more and 10 Ω·cm or less, Kurita in view of Omote discloses a p/p++ epitaxial silicon wafer (W1) comprising: the p++ silicon wafer (W0/1, 2a) as recited in claim 1; and an epitaxial layer (W0a/2b) formed on a surface of the p++ silicon wafer (W0/1, 2a), wherein the epitaxial layer (W0a/2b) has a resistivity of 1 Ω·cm or more and 10 Ω·cm or less (See Kurita ¶ 0041 and Omote ¶ 0044, ¶ 0045), where the resistivity of the epitaxial layer is adjusted in view of device requirements and constraints such as securing a depletion layer for photodiode. As to claim 4, Kurita in view of Omote further discloses having a density of oxygen precipitates formed inside the silicon wafer (W0/1, 2a) of 1×109 precipitates/cm3 or more when subjected to heat treatment for evaluation of oxygen precipitates, wherein the heat treatment comprises subjecting the p/p++ epitaxial silicon wafer (W1) to heating at 800 ºC for 3 hours and then at 1000 ºC for 16 hours in an oxygen gas atmosphere (See Kurita ¶ 0104, ¶ 0113 and Omote ¶ 0038, ¶ 0039), where the heat treatment is adjusted to provide desired properties. Claim(s) 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2009/0226737 A1 to Kurita et al. (“Kurita”), JP-2001102384-A to Ninomiya (“Ninomiya”), and U.S. Patent Application Publication No. 2011/0300371 A1 to Omote et al. (“Omote”) as applied to claim 2 above, and further in view of U.S. Patent No. 6,261,362 B1 to Fujikawa et al. (“Fujikawa”). The teachings of Kurita, Ninomiya, and Omote have been discussed above. As to claim 3, although Kurita, Ninomiya, and Omote do not further disclose the p/p++ epitaxial silicon wafer according to claim 2, having a diameter of 300 mm, wherein a light point defect (LPD) density for LPDs of 0.09 μm or more in size observable by a laser-scattering surface defect inspection device on a surface of the epitaxial layer is 5 LPDs/wafer or less, Kurita in view of Omote and Fujikawa further discloses the p/p++ epitaxial silicon wafer (W1) according to claim 2, having a diameter of 300 mm, wherein a light point defect (LPD) density for LPDs of 0.09 μm or more in size observable by a laser-scattering surface defect inspection device on a surface of the epitaxial layer (W0a/2b) is 5 LPDs/wafer or less (See Kurita ¶ 0071 and Fujikawa Fig. 4, Column 1, lines 6-12, Column 7, lines 47-67, Column 8, lines 1-15) such that a high quality wafer is obtained. As to claim 5, Kurita in view of Omote further discloses having a density of oxygen precipitates formed inside the silicon wafer (W0) of 1×109 precipitates/cm3 or more when subjected to heat treatment for evaluation of oxygen precipitates, wherein the heat treatment comprises subjecting the p/p++ epitaxial silicon wafer (W1) to heating at 800 ºC for 3 hours and then at 1000 ºC for 16 hours in an oxygen gas atmosphere (See Kurita ¶ 0104, ¶ 0113 and Omote ¶ 0038, ¶ 0039), where the heat treatment is adjusted to provide desired properties. Response to Arguments Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID CHEN/Primary Examiner, Art Unit 2815
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Prosecution Timeline

May 10, 2023
Application Filed
Jul 23, 2025
Non-Final Rejection mailed — §103
Oct 21, 2025
Response Filed
Feb 05, 2026
Final Rejection mailed — §103
Apr 30, 2026
Request for Continued Examination
May 05, 2026
Response after Non-Final Action
Jul 01, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
45%
Grant Probability
95%
With Interview (+49.9%)
3y 7m (~4m remaining)
Median Time to Grant
High
PTA Risk
Based on 686 resolved cases by this examiner. Grant probability derived from career allowance rate.

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