DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on October 21, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As to claim 1, the limitation “a resistivity of 1 mΩ·cm or more and less than 8 mΩ·cm” is not sufficiently described in the Specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Although Applicant refers to FIG. 4 for support, it appears the “8 mΩ·cm” is merely a measurement point within the originally disclosed and claimed “a resistivity of 1 mΩ·cm or more and 10 mΩ·cm or less”. As explicitly disclosed in [0020] of the Specification, the p++ silicon wafer is defined to have “an ultra-low resistivity of 1 mΩ·cm or more and 10 mΩ·cm or less”, where having 10 mΩ·cm or less provides the “high gettering ability by boron because of its high concentration in the silicon wafer”. Thus, there is no support to redefine the p++ silicon wafer to be the amended of “a resistivity of 1 mΩ·cm or more and less than 8 mΩ·cm”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2009/0226737 A1 to Kurita et al. (“Kurita”) in view of U.S. Patent Application Publication No. 2011/0300371 A1 to Omote et al. (“Omote”). As to claim 1, although Kurita discloses a silicon wafer (W0) made of monocrystalline silicon, the silicon wafer (W0) containing boron as a dopant and having a resistivity, the silicon wafer (W0) having: an oxygen concentration of 14.5×1017 atoms/cm3 or more and 16×1017 atoms/cm3 or less; and a carbon concentration of 2×1016 atoms/cm3 or more and 5×1017 atoms/cm3 or less, and the silicon wafer (W0) being free from crystal originated particles (COPs) and dislocation clusters (See Fig. 1, ¶ 0012, ¶ 0013, ¶ 0019, ¶ 0036, ¶ 0037, ¶ 0038, ¶ 0040, ¶ 0041, ¶ 0047, ¶ 0048, ¶ 0050, ¶ 0071, ¶ 0084, ¶ 0091, ¶ 0104, ¶ 0113, ¶ 0117, ¶ 0153, ¶ 0155), Kurita does not specifically disclose the silicon wafer is a p++ silicon wafer and having the resistivity of 1 mΩ·cm or more and less than 8 mΩ·cm. However, Omote does disclose the silicon wafer (1, 2a) is a p++ silicon wafer (1, 2a) and having the resistivity of 1 mΩ·cm or more and less than 8 mΩ·cm (See Fig. 1, ¶ 0004, ¶ 0005, ¶ 0017, ¶ 0019, ¶ 0029, ¶ 0032, ¶ 0038, ¶ 0039, ¶ 0044, ¶ 0045) (Notes: the p++ silicon wafer with a boron concentration of 1.06 ×1020 atoms/cm3 has a resistivity of 1.1 mΩ·cm). In view of the teachings of Kurita and Omote, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Kurita to have the silicon wafer is a p++ silicon wafer and having the resistivity of 1 mΩ·cm or more and less than 8 mΩ·cm because the p++ silicon wafer enhances aggregation of oxygen precipitates to provide high gettering capability (See Kurita ¶ 0155 and Omote ¶ 0004, ¶ 0044). As to claim 2, Kurita in view of Omote discloses a p/p++ epitaxial silicon wafer (W1) comprising: the p++ silicon wafer (W0/1, 2a) as recited in claim 1; and an epitaxial layer (W0a/2b) formed on a surface of the p++ silicon wafer (W0/1, 2a), wherein the epitaxial layer (W0a/2b) has a resistivity of 1 Ω·cm or more and 10 Ω·cm or less (See Kurita ¶ 0041 and Omote ¶ 0045), where the resistivity of the epitaxial layer is adjusted in view of device requirements and constraints such as securing a depletion layer for photodiode. As to claim 4, Kurita in view of Omote further discloses having a density of oxygen precipitates formed inside the silicon wafer (W0/1, 2a) of 1×109 precipitates/cm3 or more when subjected to heat treatment for evaluation of oxygen precipitates, wherein the heat treatment comprises subjecting the p/p++ epitaxial silicon wafer (W1) to heating at 800 ºC for 3 hours and then at 1000 ºC for 16 hours in an oxygen gas atmosphere (See Kurita ¶ 0104, ¶ 0113 and Omote ¶ 0038, ¶ 0039), where the heat treatment is adjusted to provide desired properties.
Claim(s) 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2009/0226737 A1 to Kurita et al. (“Kurita”) and U.S. Patent Application Publication No. 2011/0300371 A1 to Omote et al. (“Omote”) as applied to claim 2 above, and further in view of U.S. Patent No. 6,261,362 B1 to Fujikawa et al. (“Fujikawa”). The teachings of Kurita and Omote have been discussed above. As to claim 3, Kurita in view of Omote and Fujikawa further discloses the p/p++ epitaxial silicon wafer (W1) according to claim 2, having a diameter of 300 mm, wherein a light point defect (LPD) density for LPDs of 0.09 μm or more in size observable by a laser-scattering surface defect inspection device on a surface of the epitaxial layer (W0a/2b) is 5 LPDs/wafer or less (See Kurita ¶ 0071 and Fujikawa Fig. 4, Column 1, lines 6-12, Column 7, lines 47-67, Column 8, lines 1-15) such that a high quality wafer is obtained. As to claim 5, Kurita in view of Omote further discloses having a density of oxygen precipitates formed inside the silicon wafer (W0) of 1×109 precipitates/cm3 or more when subjected to heat treatment for evaluation of oxygen precipitates, wherein the heat treatment comprises subjecting the p/p++ epitaxial silicon wafer (W1) to heating at 800 ºC for 3 hours and then at 1000 ºC for 16 hours in an oxygen gas atmosphere (See Kurita ¶ 0104, ¶ 0113 and Omote ¶ 0038, ¶ 0039), where the heat treatment is adjusted to provide desired properties. Further, the applicant also has not established the critical nature of the “resistivity, oxygen concentration, carbon concentration, density of oxygen precipitates, diameter, LPD density for LPDs of 0.09 μm or more in size observed on a surface of the epitaxial layer is 5 LPDs/wafer or less, heat treatment parameters”. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims….In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to have various ranges. It would also have been obvious to one of ordinary skill in the art at the time the invention was made to discover the optimum or workable ranges by routine experimentations to obtain desired parameters in view of optimized device characteristics under device constraints. See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID CHEN/Primary Examiner, Art Unit 2815