Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
“5060” (see paragraph [0048] and FIG. 5).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The strikethroughs “
The descriptions of steps at paragraphs [0047] and [0048] are not accurate with the depiction in FIG. 5. See, also, the objection to the drawings above.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-21 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Perez [US 5,726,596].
As per claim 1, a digital semiconductor clocking structure [FIG. 1] comprising:
a root-clock trace [column 5, lines 7-9 first level clock buffer 102, column 5, lines 18-22 single external global clock signal CK(0) produces first level clock signal CK(1)] placed substantially perpendicular [the VLSI chip is interpreted to depict a simplistic arrangement, column 5, lines 1-3 for global data transfers between logic blocks on far ends of the chip the limitation placed substantially perpendicular is interpreted] to one end of an array of logic blocks on one of a semiconductor chip or a logical sub-block [column 5, lines 6-7 localized logic blocks 110-160] within a semiconductor block or chip [column 5, line 4 VLSI chip] having a plurality of input and output lines between bordering logic blocks [inherent to VLSI chips], the array of logic blocks having array columns and array rows [from FIG. 1 it is interpreted that an array is depicted, arrays having columns and rows is also inherent to VLSI chips];
a plurality of column-clock traces [column 5, lines 9-13 second level clock buffers 112-162 ] coupled to the root-clock trace [column 5, lines 25-29 each second level clock buffer is designed to receive CK(1) and produce CK(2) substantially in phase with CK(0)] and extending along each array column substantially in the direction of a data flow between the logic blocks [column 5, lines 9-13 arranged around, and preferably equidistant from and symmetrically about], thereby providing a clock path [column 4, lines 43-59 clocking scheme]; and
a clock buffer [column 6, lines 25-27 third level clock buffers 114-117, 124-127, 134-137, 144-147, 154-157, 164-167] in each logic block [column 4, lines 54-55 third level clock buffer may reside within each of the localized logic blocks, column 6, lines 23-27 each logic block includes third level clock buffer(s)] and configured to regenerate a clock signal on the associated column-clock trace of the plurality of column-clock traces [column 4, lines 18-22, 29-31 timing relationships, column 4, lines 43-59 clocking scheme].
2. The digital semiconductor clocking structure of claim 1, wherein the bordering logic blocks are adjacent to each other [inherent, column 1,lines 6-10 in VLSI processors, VLSI chip].
3. The digital semiconductor clocking structure of claim 1, further comprising: one or more delay buffers within a logic block and the one or more delay buffers are connected along at least one of the plurality of column-clock traces, thereby creating a clock delay [column 6, lines 23-55 the third level buffers introduce delay, column 7, lines 45-61 number of third level clock buffers may be varied, Global transfers of data across the chip].
4. The digital semiconductor clocking structure of claim 3, wherein the number of the one or more delay buffers is depends on the processes, area, temperature and voltage of the semiconductor chip [column 7, line 45-column 8, line 29 the number of third level clock buffers may be varied as required by the logical function implemented, inherent].
5. The digital semiconductor clocking structure of claim 2, wherein the one or more delay buffers are configured to provide sufficient hold times on the input and output lines between adjacent logic blocks [inherent, column 1, lines 13-26, column 4, lines 18-22, 29-31 timing relationships, column 4, lines 43-59 clocking scheme].
6. The digital semiconductor clocking structure of claim 3 wherein the clock delay is greater than the time for data to flow from the input of the adjacent logic block and the output of the adjacent logic blocks plus a flip-flop time plus a clock uncertainty time, and wherein the clock delay is less than one clock cycle plus the flip-flop hold time minus the clock uncertainty [column 4, lines 18-22, 29-31 timing relationships, column 7, lines 3-32 uncertainty is interpreted as regardless of varying RC-component induced delay or local skew, each third level buffer is load matched to its corresponding localized logic block, FIG. 5(d) deadtime, column 9, line 29-column 10, line 34 various modes of operation for overlapping or non-overlapping signals].
7. The digital semiconductor clocking structure of claim 5, wherein the number of input and output lines is greater than one-hundred [inherent, column 1,lines 6-10 in VLSI processors, VLSI chip].
8. The digital semiconductor clocking structure of claim 1, wherein the logic blocks form a data path along the column and the data path and the clock path are in the same direction [column 4, lines 18-22, 29-31 timing relationships, FIGS. 5(a)-(d) and 8].
9. The digital semiconductor clocking structure of claim 1, wherein the logic blocks form a data path along the column and the data path, and the clock path are in the opposite direction [column 4, lines 18-22, 29-31 timing relationships, FIGS. 5(a)-(d) and 8].
10. The digital semiconductor clocking structure of claim 1, wherein the root-clock trace has a single input from which a clock signal is input [column 5, lines 19-20 single external global clock signal CK(0), inherently the chip receives input].
11. The digital semiconductor clocking structure of claim 1, wherein each logic block is coupled to the respective clock trace of the plurality of clock traces from a trace tap at substantially the same location within the logic block [intersections are inherent in FIG. 1 given the symmetric arrangement].
12. A digital semiconductor clocking structure [FIG. 1] comprising:
an array of logic blocks [column 5, lines 6-7 localized logic blocks 110-160] on one of a semiconductor chip or a logical sub-block within a semiconductor chip [column 5, line 4 VLSI chip] having a plurality of input and output lines between bordering logic blocks [inherent to VLSI chips], the array of logic blocks having array columns and array rows [from FIG. 1 it is interpreted that an array is depicted, arrays having columns and rows is also inherent to VLSI chips];
a plurality of column-clock traces [column 5, lines 9-13 second level clock buffers 112-162] coupled to the root-clock trace [column 5, lines 25-29 each second level clock buffer is designed to receive CK(1) and produce CK(2) substantially in phase with CK(0)] and extending along each array column substantially in the direction of a data flow between the logic blocks [column 5, lines 9-13 arranged around, and preferably equidistant from and symmetrically about], thereby providing a clock path [column 4, lines 43-59 clocking scheme]; and
a clock buffer [column 6, lines 25-27 third level clock buffers 114-117, 124-127, 134-137, 144-147, 154-157, 164-167] in each logic block [column 4, lines 54-55 third level clock buffer may reside within each of the localized logic blocks, column 6, lines 23-27 each logic block includes third level clock buffer(s)] and configured to regenerate a clock signal on the associated column-clock trace of the plurality of column-clock traces [column 4, lines 18-22, 29-31 timing relationships, column 4, lines 43-59 clocking scheme].
13. The digital semiconductor clocking structure of claim 12, wherein the column-clock traces coupled to one of an external “H” clock tree and a balanced clock [inherent, from FIG. 1 arrangement].
14. A method for routing clock traces for an array of logic blocks on a semiconductor chip having a data flow path configured, the method comprising:
determining a data path [column 4, lines 18-22, 29-31 timing relationships, column 4, lines 43-59 clocking scheme] for each column of logic blocks [column 5, lines 6-7 localized logic blocks 110-160];
routing a column-clock trace [column 5, lines 9-13 second level clock buffers 112-162] for each column to substantially follow for each data path of each column [column 5, lines 9-13 arranged around, and preferably equidistant from and symmetrically about, column 5, lines 25-29 each second level clock buffer is designed to receive CK(1) and produce CK(2) substantially in phase with CK(0), column 4, lines 43-59 clocking scheme]; and
adding one or more clock buffer [column 6, lines 25-27 third level clock buffers 114-117, 124-127, 134-137, 144-147, 154-157, 164-167] in each logic block [column 4, lines 54-55 third level clock buffer may reside within each of the localized logic blocks, column 6, lines 23-27 each logic block includes third level clock buffer(s)] configured to regenerate a clock signal on the associated column-clock trace [column 4, lines 18-22, 29-31 timing relationships, column 4, lines 43-59 clocking scheme].
15. The method for routing clock traces of claim 14, wherein the logic blocks are adjacent to each other [as depicted in FIG. 1].
16. The method for routing clock traces of claim 14, further comprising: adding one or more delay buffers within a logic block and the one or more delay buffers are connected along at least one of the plurality of column-clock traces, thereby creating a clock delay between the logic block clock and an adjacent logic block [column 6, lines 23-55 the third level buffers introduce delay, column 7, lines 45-61 number of third level clock buffers may be varied, Global transfer s of data across the chip].
17. The method for routing clock traces of claim 16, wherein the clock delay is greater than the time for data to flow from the input of the adjacent block and the output of the adjacent logic block plus a flip-flop time plus a clock uncertainty time, and wherein the clock delay is less than one clock cycle plus the flip-flop hold time minus the clock uncertainty [column 4, lines 18-22, 29-31 timing relationships, column 7, lines 3-32 uncertainty is interpreted as regardless of varying RC-component induced delay or local skew, each third level buffer is load matched to its corresponding localized logic block, FIG. 5(d) deadtime, column 9, line 29-column 10, line 34 various modes of operation for overlapping or non-overlapping signals].
18. The method for routing clock traces of claim 17, wherein the array of logic blocks have a input and output lines between adjacent logic blocks [inherent to VLSI chips, FIG. 1] and wherein the number of input and output lines is greater than one-hundred [inherent, column 1,lines 6-10 in VLSI processors, VLSI chip].
19. The method for routing clock traces of claim 14, the method further comprising adding a row clock trace positioned substantially perpendicular to one end of the array of logic blocks on a semiconductor chip [column 5, lines 9-11 any of the second level clock buffers 122-162 each corresponding to a localized logic block 110-160, the VLSI chip in FIG. 1 is interpreted to depict a simplistic arrangement, column 5, lines 1-3 for global data transfers between logic blocks on far ends of the chip the limitation placed substantially perpendicular is interpreted].
20. The method for routing clock traces of claim 19, wherein the root-clock trace has a single input from which a clock signal is input [column 5, lines 19-20 single external global clock signal CK(0), inherently the chip receives input].
21. The method for routing clock traces of claim 14, wherein each logic block is coupled to the respective clock trace of the plurality of clock traces from a trace tap at substantially the same location within the logic block [intersections are inherent in FIG. 1 given the symmetric arrangement].
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See, for example, Vo et al. [US 9,300,294 B2] at FIGS. 4A-B, column 6, line 48-column 8, line 7; Kuang et al. [US 2023/0016311 A1] at Abstract; Hwang et al. [US 7,941,689 B2] at entire document; Kitagawa et al. [US 6,788,109 B2] at entire document; Faue [US 7,830,734 B2] at column 4, lines 39-53; Andreev et al. [US 8,629,548 B1] at FIGS. 2C-E; Bergendahl et al. [US 7,353,487 B1] at entire document; Fukuoka et al. [US 7,629,827 B2] at entire document; Debnath et al. [US 5,564,022] at entire document, particularly step (b) of claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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/LEIGH M GARBOWSKI/Primary Examiner, Art Unit 2851