DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species XIX (corresponds to re-listed species X below), claims 1-20, in the reply filed on November 24, 2025 is acknowledged. The traversal is on the ground(s) that “the present 64-way election of species is unduly granular and is not supported by a showing that the alleged species are distinct in the sense of requiring separate searches or presenting different inventions” and “the Office should consolidate the alleged species that share the same figures and overlapping disclosure into a single elected group”. This is found persuasive. Therefore, for clarification, the patentable distinct species are re-listed as follows:
I: Figs. 1, 5, 6.
II: Figs. 2, 5, 6.
III: Figs. 3, 5, 6.
IV: Figs. 4, 7, 6 and [0065]-[0067].
V: Figs. 1, 8, 9.
VI: Figs. 2, 8, 9.
VII: Figs. 3, 8, 9.
VIII: Figs. 4, 8, 9.
IX: Figs. 1, 8, 10.
X: Figs. 2, 8, 10.
XI: Figs. 3, 8, 10.
XII: Figs. 4, 8, 10.
XIII: Figs. 1, 11, 12.
XIV: Figs. 2, 11, 12.
XV: Figs. 3, 11, 12.
XVI: Figs. 4, 11, 12.
XVII: Figs. 1, 11, 13.
XVIII: Figs. 2, 11, 13.
XIX: Figs. 3, 11, 13.
XX: Figs. 4, 11, 13.
XXI: Figs. 1, 14, 15.
XXII: Figs. 2, 14, 15.
XXIII: Figs. 3, 14, 15.
XXIV: Figs. 4, 14, 15.
XXV: Figs. 1, 16, 17.
XXVI: Figs. 2, 16, 17.
XXVII: Figs. 3, 16, 17.
XXVIII: Figs. 4, 16, 17.
XXIX: Figs. 1, 16, 17.
XXX: Figs. 2, 16, 17.
XXXI: Figs. 3, 16, 17.
XXXII: Figs. 4, 16, 17.
XXXIII: Figs. 1, 18, 19.
XXXIV: Figs. 2, 18, 19.
XXXV: Figs. 3, 18, 19.
XXXVI: Figs. 4, 18, 19.
The requirement is still deemed proper and is therefore made FINAL.
Claims 10-15 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species. There is no support in the elected embodiment of Figs. 2, 8 and 10 for the claim limitations of “a data storage layer between the first dielectric layer and the second dielectric layer”, as recited in claim 10; “a semiconductor pattern on the substrate, wherein the semiconductor pattern includes a first source/drain region, a second source/drain region farther than the first source/drain region from the substrate, and the channel region between the first source/drain region and the second source/drain region, the conductive electrode is on a side surface of the semiconductor pattern, and the data storage structure is between the side surface of the semiconductor pattern and the conductive electrode”, as recited in claim 12; “the conductive electrode is on a first surface of the channel region, a second surface of the channel region perpendicular to the first surface of the channel region, and a third surface of the channel region perpendicular to the first surface of the channel region, and the second and third surfaces of the channel region are opposite surfaces of the channel region”, as recited in claim 13; “the channel region is a first channel region of a plurality of channel regions that are included in respective active layers between the source region and the drain region and spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, the conductive electrode encloses the active layers, and the data storage structure is a first data storage structure of a plurality of data storage structures between the active layers and the conductive electrode”, as recited in claim 14; and “a stack structure on the substrate, including interlayer insulating layers and gate electrodes stacked alternately and repeatedly in a vertical direction; and a vertical memory structure extending in the stack structure in the vertical direction, wherein the vertical memory structure includes: an insulating core pattern; a channel layer on an outer side surface of the insulating core pattern; and a pad pattern on an upper surface of the insulating core pattern”, as recited in claim 15; these features are found on unelected embodiment of Figs. 4, 17, 13, 15 and 6, respectively.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed May 10, 2023 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Specification
The disclosure is objected to because of the following informalities: “x” should be in subscript (first occurrence: [0015], line 5); “2” and “3” should be in subscript (first occurrence: [0018], lines 4 and 5); and “540” should read “640” ([0106], line 3).
Appropriate correction is required.
Claim Objections
Claims 1-9 and 16-20 are objected to because of the following informalities: a comma should be inserted after “device” (claims 1, 17 and 19, line 1); and “,” should read “:” after “includes” (claim 16, line 1). Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of "the vertical memory structure further includes protruding areas extending toward the conductive lines in a horizontal direction between the interlayer insulating layers", as recited in claim 16, is unclear as to which element between the interlayer insulating layers applicant refers.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peng et al. (2021/0313440).
As for claim 1, Peng et al. show in Fig. 1C (or 1E) and related text a memory device comprising:
a channel region 1C;
a conductive electrode 6 on the channel region; and
a data storage structure 2/STK_3 (or 2/STK_5) between the channel region and the conductive electrode,
wherein the data storage structure includes a first dielectric layer 2 and a second dielectric layer STK_4 (or STK_5) on the first dielectric layer,
the second dielectric layer includes a ferroelectric region 4x (or upper portion of 4) and a barrier dielectric region 4y/5y (or 5/lower portion (interface region between 4 and 5)) on the ferroelectric region, the ferroelectric region includes a first material (Hf), and the barrier dielectric region includes a second material (HfON) comprising a compound of the first material and oxygen or a compound of the first material and nitrogen.
As for claim 2, Peng et al. show the first dielectric layer is in contact with the channel region, and the barrier dielectric region is in contact with the conductive electrode (Fig. 1C).
As for claim 3, Peng et al. show the ferroelectric region comprises the first material in a first crystalline phase ([0035]), and
the barrier dielectric region comprises the second material in a second crystalline phase different from the first crystalline phase ([0039]).
As for claim 4, Peng et al. show the first crystalline phase includes an orthorhombic phase (O-phase) ([0035]), and
the second crystalline phase includes a monoclinic phase (M-phase) ([0039]).
As for claim 5, Peng et al. show the second material of the barrier dielectric region comprises a nitride of the first material, and a nitrogen concentration of the barrier dielectric region decreases in a direction from the conductive electrode toward the channel region (Fig. 1C).
As for claim 6, Peng et al. show the second material of the barrier dielectric region comprises an oxide of the first material, and
an oxygen concentration of the barrier dielectric region decreases in a direction from the conductive electrode toward the channel region (Fig. 1E).
As for claim 7, Peng et al. show the barrier dielectric region includes a first sub-barrier dielectric region (HfON: lower portion of 5y) and a second sub-barrier dielectric region on the first sub-barrier dielectric region (upper portion of 5y) (Fig. 1C).
As for claim 8, Peng et al. show the first sub-barrier dielectric region includes a third material comprising a nitride of the first material (HfON: lower portion of 5y), and
the second sub-barrier dielectric region includes a fourth material comprising an oxide of the third material (upper portion of 5y) (Fig. 1C).
As for claim 9, Peng et al. show the first sub-barrier dielectric region includes a third material comprising an oxide of the first material (HfON: lower portion of 5y), and
the second sub-barrier dielectric region includes a fourth material comprising a nitride of the third material (upper portion of 5y) (Fig. 1C).
As for claim 19, Peng et al. show in Fig. 1C and related text a memory device comprising:
a channel region 1C;
a conductive electrode 6 on the channel region; and
a data storage structure 2/STK_3 between the channel region and the conductive electrode,
wherein the data storage structure includes a first dielectric layer 2 in contact with the channel region, and a second dielectric layer STK_3 on the first dielectric layer,
the second dielectric layer includes a ferroelectric region 4x and a high-k region on the ferroelectric region 5y/4y, the ferroelectric region includes a first material (Hf),
the high-k region includes a second material (HfON) comprising a compound of the first material and oxygen or a compound of the first material and nitrogen, and
a concentration of the oxygen or nitrogen in the high-k region decreases in a direction from the conductive electrode toward the channel region.
As for claim 20, Peng et al. show a thickness of the high-k region is in a range from 5 angstroms (Å) to 15 Å ([0042]), and
the high-k region extends from the ferroelectric region and contacts the conductive electrode (Fig. 1C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (2021/0313440).
As for claim 17, Peng et al. show in Fig. 1C and related text a memory device comprising:
a channel region 1C;
a conductive electrode 6 on the channel region; and
a data storage structure 2/STK_3 between the channel region and the conductive electrode,
wherein the data storage structure includes a first dielectric layer 2 on the channel region and a second dielectric layer STK_3 on the first dielectric layer, the second dielectric layer includes a data storage region 4x and a barrier dielectric region 4y/5y on the data storage region,
the data storage region includes a first material (Hf),
the barrier dielectric region includes a second material (HfON) comprising a compound of the first material and oxygen or a compound of the first material and nitrogen, a concentration of the oxygen or nitrogen in the barrier dielectric region decreases in a direction from the conductive electrode toward the channel region, and
a thickness of the barrier dielectric region is in a range from 5 Å to 15 Å ([0042]).
Peng et al. do not disclose a thickness of the data storage region is in a range from 100 angstroms (Å) to 200 Å.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a thickness of the data storage region being in a range from 100 angstroms (Å) to 200 Å, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
As for claim 18, Peng et al. show the first dielectric layer is in a range from 8 Å to 20 Å ([0036]),
the first material comprises a ferroelectric material ([0035]), and
the second material comprises a high-k dielectric material ([0039]).
Allowable Subject Matter
Claim 16 is allowed.
Claim 16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of “a stack structure on the substrate; and a vertical memory structure extending in the stack structure in a vertical direction, wherein the stack structure includes interlayer insulating layers and conductive lines alternately and repeatedly stacked in the vertical direction, the vertical memory structure includes the conductive electrode, the vertical memory structure further includes protruding areas extending toward the conductive lines in a horizontal direction and between the interlayer insulating layers, respectively, each protruding area comprises a portion of the conductive electrode, the data storage structure on the portion of the conductive electrode, and the channel region on the data storage structure, and the portion of the conductive electrode is spaced apart from a respective one of the conductive lines by the data storage structure and the channel region”, as recited in claim 16.
Conclusion
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/MEIYA LI/Primary Examiner, Art Unit 2811
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