DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/11/23 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 26-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 26 recites “A method of manufacturing an RF package assembly comprising a stacked arrangement of a first substrate and a second substrate, the method comprising: providing a first substrate…; providing a second substrate…” (emphasis added). It is unclear what is the difference between the “a first substrate” recited in the preamble and the “a first substrate” recited in the body of the claim. The same issue applies to “a second substrate”. The Examiner has assumed “the first substrate” and “the second substrate” in the body of the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16-18, 22-24 and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ueda (US 2018/0084637).
a. Re claim 16, Ueda discloses a radio frequency (RF) package assembly comprising a stacked arrangement of a first substrate 10 and a second substrate 30 (see figs. 1-3B and related text; see [0054]-[0070]; see remaining of disclosure for more details), wherein: the first substrate has a first substrate interface layer (made of pads 21, 22 and 23) which includes a plurality of first substrate RF signal pads 21 ([0055]) configured (i.e. capable) to transmit or receive an RF signal, and a plurality of first substrate ground pads 22 ([0055]); the second substrate has a second substrate interface layer (made of pads 41, 42 and 43) which includes a plurality of second substrate RF signal pads 41 ([0058]) configured (i.e. capable) to transmit or receive an RF signal, and a plurality of second substrate ground pads 42 ([0058]); and the RF package assembly further includes an interface region (gap region between 31 and 11 including everything in said gap to the exclusion of pads 21-23 and 41-43) between the first substrate and the second substrate, wherein the interface region includes a plurality of galvanic connection regions 50 (solder bumps as in Applicants’ invention; see [0060]) providing a galvanic connection between the plurality of first substrate ground pads and the plurality of second substrate ground pads, and a plurality of dielectric regions DR (see annotated fig. 1 below wherein a dielectric region is a region in the footprint of a gap between a pad 21 and a corresponding pad 41, wherein such a gap comprises portions of insulating layers 26 and 46, or a combination of said portions of insulating layers 26 and 46 and an air gap therebetween, and there are a plurality of said dielectric regions as per fig. 1) between the plurality of first substrate RF signal pads and the plurality of second substrate RF signal pads.
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b. Re claim 17, the RF package assembly is configured to capacitively couple an RF signal transmitted between the first substrate and the second substrate via a respective one of the plurality of the first substrate RF signal pads and a respective one of the plurality of the second substrate RF signal pads (see at least [0061]).
c. Re claim 18, at least one of the plurality of first substrate RF signal pads and the plurality of second substrate RF signal pads extends into the interface region (explicit on fig. 1 in view of how the interface region is defined in claim 1 rejection above).
d. Re claim 22, a dielectric material (air gap between 26 and 46 in DR regions of annotated fig. 1) in the plurality of dielectric regions comprises air.
e. Re claim 23, a dielectric region of the plurality of dielectric regions defines a minimum separation between the first substrate RF signal pads and the second substrate RF signal pads (explicit on annotated fig. 1).
f. Re claim 24, each of the plurality of galvanic connection regions comprises (i.e. is) a solder connection (50 is a solder bump) between the first substrate ground pads and the second substrate ground pads.
g. Re claim 26, Ueda discloses a method of manufacturing an RF package assembly comprising a stacked arrangement of a first substrate 10 and a second substrate 30 (see figs. 1-3B and related text; see [0054]-[0070]; see remaining of disclosure for more details), the method comprising: providing the first substrate having a first substrate interface layer (made of pads 21, 22 and 23) that includes a plurality of first substrate RF signal pads 21 configured to transmit or receive an RF signal, and a plurality of first substrate ground pads 22; providing the second substrate having a second substrate interface layer (made of pads 41, 42 and 43) that includes a plurality of second substrate RF signal pads 41, and a plurality of second substrate ground pads 42; and forming an interface region (gap region between 31 and 11 including everything in said gap to the exclusion of pads 21-23 and 41-43) between the first substrate and the second substrate by forming a plurality of galvanic connection regions 50 (solder bumps as in Applicants’ invention) connecting the plurality of first substrate ground pads and the plurality of second substrate ground pads, and forming a plurality of dielectric regions DR (as defined and explained in claim 1 rejection and annotated fig. 1 above) between the plurality of first substrate RF signal pads and the plurality of second substrate RF signal pads.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20-22, 25, 27-28 and 31-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ueda (US 2018/0084637).
a. Re claim 20, Ueda discloses all the limitations of claim 16 as stated above except explicitly that the first substrate RF signal pads are thicker than the first substrate ground pads. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided, via a non-inventive change in size (see MPEP 2144.04.IV), the first substrate RF signal pads to be thicker than the first substrate ground pads in order to make the RF signal pads 21 closer to the RF signal pads 41 for faster RF signal transmission, thereby obtaining a faster and more efficient device 1 (see MPEP 2144.I&II).
b. Re claim 21, Ueda discloses all the limitations of claim 16 as stated above except explicitly that the second substrate RF signal pads are thicker than the second substrate ground pads. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided, via a non-inventive change in size (see MPEP 2144.04.IV), the second substrate RF signal pads to be thicker than the second substrate ground pads in order to make the RF signal pads 41 closer to the RF signal pads 21 for faster RF signal transmission, thereby obtaining a faster and more efficient device 1 (see MPEP 2144.I&II).
c. Re claim 22, and in the alternative to the anticipation rejection based on fig. 1 taking into account [0061] wherein the possibility of an underfill filled between 10 and 30 exists, it would have been obvious to one skilled in the art before the effective filing date of the invention to have omitted the underfill in order to save cost and time (see MPEP 2144.I&II), resulting in the dielectric comprising air (air gap between 26 and 46 in DR regions of annotated fig. 1).
d. Re claim 25, Ueda discloses an antenna-in-package comprising: a radio frequency (RF) package assembly that includes a stacked arrangement of a first substrate 10 and a second substrate 30 (see figs. 1-3B and related text; see [0054]-[0070]; see remaining of disclosure for more details), wherein the first substrate has a first substrate interface layer (made of pads 21, 22 and 23) which includes a plurality of first substrate RF signal pads 21 configured (i.e. capable) to transmit or receive an RF signal, a plurality of first substrate ground pads 22, and an antenna array layer comprising an array of antennas 13 ([0055]), wherein the plurality of first substrate RF signal pads are coupled (via transmission lines 15) to respective patch antennas of the array of antennas; the second substrate has a second substrate interface layer (made of pads 41, 42 and 43) which includes a plurality of second substrate RF signal pads 41 configured (i.e. capable) to transmit or receive an RF signal, and a plurality of second substrate ground pads 42; and the RF package assembly further includes an interface region (gap region between 31 and 11 including everything in said gap to the exclusion of pads 21-23 and 41-43) between the first substrate and the second substrate, wherein the interface region includes a plurality of galvanic connection regions 50 (solder bumps as in Applicants’ invention) providing a galvanic connection between the plurality of first substrate ground pads and the plurality of second substrate ground pads, and a plurality of dielectric regions DR (as defined in claim 1 rejection and annotated fig. 1 above) between the plurality of first substrate RF signal pads and the plurality of second substrate RF signal pads. But Ueda does not appear to explicitly disclose the antennas 13 to be patch antennas. However, patch antennas are conventionally known in the art, and as such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the antennas 13 to be patch antennas for an application of device 1 requiring such types of antennas.
e. Re claim 27, Ueda discloses all the limitations of claim 26 as stated above including that forming a plurality of galvanic connection regions to connect the plurality of first substrate ground pads and the plurality of second substrate ground pads comprises: creating solder connections (solder of solder bumps 50) for the plurality of first substrate ground pads, except explicitly for applying at least one of solder and anisotropic conductive paste to the plurality of second substrate ground pads. However, it is conventionally known in the art to provide solder paste on pads of a first and second electronic devices in order to hold in place solder bumps disposed on and between said pads prior to bonding said first and second electronic devices, thereby minimizing any lateral displacement between said first and second electronic devices. As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have applied solder paste to at least the plurality of second substrate ground pads (and also to all the remaining pads of said second substrate and first substrate as necessary) in order to hold in place the solder bumps (or solder connections) 50 prior to bonding with the first substrate pads as would have been conventionally done in the art (see MPEP 2144.I&II).
f. Re claim 28, Ueda discloses all the limitations of claim 26 as stated above including that forming a plurality of galvanic connection regions to connect the plurality of first substrate ground pads and the plurality of second substrate ground pads comprises: creating solder connections (solder of solder bumps 50) for the plurality of second substrate ground pads, except explicitly for applying at least one of solder and anisotropic conductive paste to the plurality of first substrate ground pads. However, it is conventionally known in the art to provide solder paste on pads of a first and second electronic devices in order to hold in place solder bumps disposed on and between said pads prior to bonding said first and second electronic devices, thereby minimizing any lateral displacement between said first and second electronic devices. As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have applied solder paste to at least the plurality of second substrate ground pads (and also to all the remaining pads of said second substrate and first substrate as needed) in order to hold in place the solder bumps (or solder connections) 50 prior to bonding with the first substrate pads as would have been conventionally done in the art (see MPEP 2144.I&II).
g. Re claim 31, Ueda discloses an antenna-in-package package assembly comprising a stacked arrangement of a first substrate 10 and a second substrate 30 (see figs. 1-3B and related text; see [0054]-[0070]; see remaining of disclosure for more details), wherein: the first substrate includes an antenna array layer (layers 13) with [an] antenna (any one antenna 13), and a first substrate interface layer (made of pads 21, 22 and 23) which includes a first substrate RF signal pad 21 coupled to the antenna, and a first substrate ground pad 22; the second substrate includes a second substrate interface layer (made of pads 41, 42 and 43) which includes a second substrate RF signal pad 41, and a second substrate ground pad 42; the antenna-in-package package assembly further includes an interface region (gap region between 31 and 11 including everything in said gap to the exclusion of pads 21-23 and 41-43) between the first substrate and the second substrate, the interface region configured and arranged to galvanically connect (via solder bumps 50) the first substrate ground pad to the second substrate ground pad, and further configured to capacitively couple (via dielectric regions DR on annotated fig. 1 above; see also [0061]) an RF signal transmitted between the first substrate and the second substrate via the first substrate RF signal pad and the second substrate RF signal pad. But Ueda does not appear to explicitly disclose the antennas 13 to be patch antennas. However, patch antennas are conventionally known in the art, and as such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the antennas 13 to be patch antennas for an application of device 1 requiring such types of antennas.
h. Re claim 32, the interface region further comprises: a galvanic connection region 50 providing a galvanic connection between the first substrate ground pad and the second substrate ground pad; and a dielectric region DR (see annotated fig. 1 and claim 1 rejection above) between the first substrate RF signal pad and the second substrate RF signal pad.
i. Re claim 33, see claim 2 rejections above.
j. Re claim 34, see claim 18 rejection above.
Allowable Subject Matter
Claims 19, 29-30 (this assumes the 112 2nd issue of independent claim 26 is resolved) and 35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Garcia et al. (US 2016/0056544) and Zhao et al. (US 2013/0082363) disclose structures similar to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899