Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a) (2) being anticipated by the prior art of record Park (US 2023/0153506)
Regarding claim 1, the prior art discloses:
A method of placing flexible blocks on a chip canvas (see place/layout macros, semiconductor elements in on chip canvas/ floorplan in one or more of abstract, fig 1, 16, 20 ) in an IC design, comprising:
receiving, by a neural network (see one or more of abstract, fig 16, 17, 20), an input describing geometric features of a flexible block to be placed on the chip canvas, the geometric features including an area size (see one or more of par 8, 43-48, 54, 76, 84, 90, 93, 102-103, 109) and a plurality of aspect ratios (see one or more of par 43-48, 54, 76, 84, 90, 93, 102-103, 109) and/or fig 7-15 disclosed aspect ratios of macros/ semiconductor elements placed on canvas/floorplane/ chip grid);
generating, by the neural network, a probability distribution over locations (see one or more of abstract, fig 17, 20) on the chip canvas and the aspect ratios of the flexible block; and
selecting a location on the chip canvas for placing the flexible block with a chosen aspect ratio based on the probability distribution (see one or more of fig 1, 7-16, par 12-14, 54, 76, 79, 88, 90).
(Claim 2) generating action masks(par 79-80) for respective ones of the aspect ratios of the flexible block, each action mask to block out a region of the chip canvas for a corresponding aspect ratio.
(Claim 3) wherein each action mask is to block out the region in which placement of the flexible block violates a non-overlapping constraint (par 79-80).
(Claim 4) applying action masks to the probability distribution to generate a masked distribution, wherein regions of the chip canvas that are blocked out by the action masks are set to a probability value of zero (par 79-80).
(claim 5) after placement of all of the flexible blocks on the chip canvas, calculating a wirelength measurement based on wire connections of the flexible blocks (see one or more of par 18-19, 45-47, 54, 81-91, 102).
(Claim 6) calculating a wirelength measurement for each of a plurality of floorplans, each floorplan corresponding to a different placement of the flexible blocks and fixed blocks on the chip canvas; and selecting one of the floorplans that minimizes the wirelength measurement (see one or more of par 18-19, 45-47, 54, 81-91, 102).
(Claim 7) wherein the chip canvas is represented by a grid of a plurality of equal-sized grid cells, the method further comprises: generating an action mask to block out the grid cells in which placement of the flexible block violates a density threshold that specifies a maximum sum of occupied areas in each grid cell (par 88-92, 104-105)
(Claim 8) wherein the occupied areas in each grid cell include areas occupied by fixed blocks (i.e., macro cells/ semiconductor elements at an edge of the canvas, placed by size/type (par 48, 76) )and the flexible blocks.
(Claim 9) wherein the chip canvas is represented by a grid of a plurality of equal-sized grid cells, the method further comprises: generating the probability distribution over an action space, the size of the action space defined by the size of the grid and the number of the aspect ratios of the flexible block (fig 6-15).
(Claim 10) wherein the neural network includes a graph neural network, fully-connected networks, and deconvolution networks (par 11, 69. 101, 107)
Claims 11-20 recite similar subject matter and are rejected for the same reason,
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/ Primary Examiner, Art Unit 2851